公开(公告)号：US5379264A

公开(公告)日：1995-01-03

申请号：US214161

申请日：1994-03-17

申请人： Kazuya Kobayashi ,  Kiyoshi Miyasaka ,  Junji Ogawa

发明人： Kazuya Kobayashi ,  Kiyoshi Miyasaka ,  Junji Ogawa

IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C8/00 ,  G06F12/00 ,  G09G1/02 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/1006

摘要： A semiconductor memory device enables multi-direction data access at a high speed with a simple circuit construction. The semiconductor memory device includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells connected to the bit lines and word lines. A row decoder, connected to the word lines, selects one of the word lines in response to a row address signal. A selection circuit includes a plurality of column decoders and a direction decoder. Each column decoder receives a portion of a column address signal and the direction decoder selects one of three directions in response to a direction address signal. Each column decoder is selectively enabled based upon the direction address signal. Output circuitry outputs data read out from bit lines selected by the enabled column decoders. Thus, three-dimensional bit map data can be stored in two dimensions.

摘要翻译： 半导体存储器件能够以简单的电路结构高速地进行多方向数据存取。 半导体存储器件包括多个字线，多个位线和连接到位线和字线的多个存储器单元。 连接到字线的行解码器响应于行地址信号选择字线之一。 选择电路包括多个列解码器和方向解码器。 每列解码器接收列地址信号的一部分，并且方向解码器响应于方向地址信号选择三个方向之一。 基于方向地址信号来选择性地使能每一列解码器。 输出电路输出从使能列解码器选择的位线读出的数据。 因此，三维位图数据可以存储在二维中。

公开(公告)号：US4752914A

公开(公告)日：1988-06-21

申请号：US739159

申请日：1985-05-30

申请人： Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Kimiaki Sato ,  Norihisa Tsuge ,  Itaru Tsuge ,  Sachie Tsuge

发明人： Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Kimiaki Sato ,  Norihisa Tsuge ,  Itaru Tsuge ,  Sachie Tsuge

IPC分类号： G11C29/00 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C29/835

摘要： A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion and for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit for detecting coincidence between data read from the memory unit and a received input address. Data produced from the comparison by the comparison unit is delivered through an external connection terminal.

摘要翻译： 一种半导体集成电路，包括存储单元，用于存储故障电路部分的地址信息，并通过冗余电路部分来替换故障电路部分。 半导体集成电路提供用于检测从存储单元读取的数据与接收到的输入地址之间的一致性的比较单元。 通过比较单元的比较产生的数据通过外部连接终端传送。

公开(公告)号：US4745577A

公开(公告)日：1988-05-17

申请号：US798284

申请日：1985-11-15

申请人： Junji Ogawa ,  Yoshihiro Takemae

发明人： Junji Ogawa ,  Yoshihiro Takemae

IPC分类号： H01L27/08 ,  G11C7/10 ,  G11C19/00 ,  G11C7/00

CPC分类号： G11C7/1075

摘要： A semiconductor memory device with shift registers used for a video RAM, including a memory cell array, bit lines, and word lines, a pair of shift registers, and transfer gate circuits arranged between the bit lines and the shift registers. Each parallel data transfer circuit is provided between the shift registers for transferring parallel data between the shift registers, so that high-speed reading and writing of data for a CRT display is realized.

摘要翻译： 具有用于视频RAM的移位寄存器的半导体存储器件，包括存储单元阵列，位线和字线，一对移位寄存器和布置在位线和移位寄存器之间的传输门电路。 每个并行数据传输电路设置在用于在移位寄存器之间传送并行数据的移位寄存器之间，从而实现用于CRT显示器的数据的高速读取和写入。

公开(公告)号：US4707806A

公开(公告)日：1987-11-17

申请号：US712149

申请日：1985-03-15

申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Masao Nakano ,  Norihisa Tsuge, deceased

发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Masao Nakano ,  Norihisa Tsuge, deceased

IPC分类号： H01L27/00 ,  G11C8/10 ,  G11C17/14 ,  G11C17/16 ,  G11C29/00 ,  G11C29/04 ,  H01L23/525 ,  G11C11/00

CPC分类号： G11C29/785 ,  G11C17/16 ,  G11C8/10 ,  H01L23/5256 ,  H01L2924/0002

摘要： A device connected between first and second voltage feed lines includes an information storing circuit having a fuse for storing information by blowing or not blowing the fuse, a voltage level conversion circuit connected to at least one of the first and second voltage feed lines and outputting a voltage lower than a voltage between the first and second voltage feed lines to the information storing circuit, and a circuit connected between the first and second voltage feed lines, for outputting a detection signal in response to a voltage value at the fuse in the information storing circuit to which the voltage is applied from the voltage level conversion circuit and which voltage value is varied with the blown or unblown state of the fuse.In a normal operation, the voltage output from the voltage level conversion circuit can be set as low as possible to restrain electromigration caused at the vicinity of the blown portion of the fuse to which the voltage is applied, but higher than the threshold voltage of the information detection circuit.

摘要翻译： 连接在第一和第二电压馈送线之间的装置包括信息存储电路，该信息存储电路具有熔丝，用于通过吹送或不熔断熔丝来存储信息;电压电平转换电路，连接到第一和第二电压馈送线中的至少一个并输出一个 电压低于第一和第二电压馈送线之间的电压到信息存储电路，以及电路，连接在第一和第二电压馈送线之间，用于响应于信息存储中的熔丝处的电压值输出检测信号 从电压电平转换电路向其施加电压的电路，以及哪个电压值随着保险丝的熔断或非吹出状态而变化。 在正常操作中，可以将从电压电平转换电路输出的电压设置得尽可能低以抑制在施加电压的熔丝的熔断部分附近引起的电迁移，但是高于 信息检测电路。

公开(公告)号：US4616343A

公开(公告)日：1986-10-07

申请号：US788049

申请日：1985-10-16

申请人： Junji Ogawa

发明人： Junji Ogawa

IPC分类号： G11C7/00 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4096 ,  H01L27/10 ,  G11C11/40 ,  G11C13/00

CPC分类号： G11C11/4096 ,  G11C11/4094

摘要： A semiconductor memory device including a random access memory cell array, a series/parallel data transfer circuit, transfer gate, an active pull-up circuit, and an active pull-down circuit. The transfer gate is inserted between bit lines of the random access memory cell array and the series/parallel data transfer circuit to carry out parallel transfer of data. Output data of the series/parallel data transfer circuit is simultaneously written in a group of memory cells of selected work lines by turning on the transfer gate and selection of a word line. When data of each output of steps of the series/parallel data transfer circuit is logic "1", the active pull-up circuit charges up a selected bit line of the random access memory cell array. When data of each output of steps of the series/parallel data transfer circuit is logic "0", the active pull-down circuit discharges a selected bit line of the random access memory cell array. One or more of the active pull-up and active pull-down circuits is arranged in the semiconductor memory device.

摘要翻译： 包括随机存取存储单元阵列，串联/并行数据传输电路，传输门，有源上拉电路和有源下拉电路的半导体存储器件。 传输门被插入到随机存取存储单元阵列的位线和串/并行数据传输电路之间，以执行数据的并行传输。 串行/并行数据传输电路的输出数据通过接通传输门和选择字线而被同时写入选定工作线的一组存储单元。 当串/并行数据传输电路的每个输出的数据为逻辑“1”时，有源上拉电路对随机存取存储单元阵列的所选位线充电。 当串联/并行数据传送电路的每个输出的数据为逻辑“0”时，有源下拉电路对所选择的随机存取存储单元阵列的位线进行放电。 有源上拉和有源下拉电路中的一个或多个布置在半导体存储器件中。

公开(公告)号：US08949511B2

公开(公告)日：2015-02-03

申请号：US13379223

申请日：2011-09-30

申请人： Atsushi Ishikawa ,  Koji Sonoda ,  Go Uehara ,  Junji Ogawa ,  Hideyuki Koseki

发明人： Atsushi Ishikawa ,  Koji Sonoda ,  Go Uehara ,  Junji Ogawa ,  Hideyuki Koseki

IPC分类号： G06F12/02 ,  G06F13/16 ,  G06F3/06

CPC分类号： G06F3/0608 ,  G06F3/0626 ,  G06F3/0635 ,  G06F3/0647 ,  G06F3/0658 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0246 ,  G06F13/16 ,  G06F13/1684 ,  G06F13/4022

摘要： A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus. The switch is configured so as to switch a coupling between a data bus coupled to the media interface group and a data bus coupled to any of multiple nonvolatile chips that are coupled to this switch. The control circuit partitions write-target data into multiple data elements, switches a coupling by controlling the multiple switches, and distributively sends the multiple data elements to multiple nonvolatile chips.

摘要翻译： 非易失性半导体存储系统具有多个非易失性半导体存储介质，具有耦合到多个非易失性半导体存储介质的介质接口组（一个或多个接口器件）和多个开关的控制电路。 介质接口组和多个开关经由数据总线耦合，并且每个开关和两个或更多个非易失性芯片中的每一个经由数据总线耦合。 该开关被配置为切换耦合到媒体接口组的数据总线与耦合到耦合到该开关的多个非易失性芯片中的任何一个的数据总线之间的耦合。 控制电路将写目标数据分成多个数据元，通过控制多个开关切换耦合，并将多个数据元素分配发送到多个非易失性芯片。

公开(公告)号：US08762638B2

公开(公告)日：2014-06-24

申请号：US13379186

申请日：2011-12-08

申请人： Junichi Hara ,  Junji Ogawa

发明人： Junichi Hara ,  Junji Ogawa

IPC分类号： G11C29/00 ,  G06F11/10

CPC分类号： G06F3/065 ,  G06F3/0626 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0685 ,  G06F3/0689 ,  G06F11/1076 ,  G06F2212/401

摘要： A first storage system comprises a first RAID group comprising multiple first storage devices, which constitute the basis of a first logical volume. A second storage system comprises a second RAID group comprising multiple second storage devices, which constitute the basis of a second logical volume. The RAID configuration of the first RAID group and the RAID configuration of the second RAID group are the same, and the type of a compression/decompression function of the respective first storage devices and the type of a compression/decompression function of the respective second storage devices are the same. Compressed data is read from a first storage device without being decompressed with respect to the data inside a first logical volume, and the read compressed data is written to a second storage device, which is in the same location in RAID in the second RAID group as the location in RAID of this first storage device.

摘要翻译： 第一存储系统包括构成第一逻辑卷的基础的多个第一存储设备的第一RAID组。 第二存储系统包括构成第二逻辑卷的基础的多个第二存储设备的第二RAID组。 第一RAID组的RAID配置和第二RAID组的RAID配置是相同的，并且相应的第一存储设备的压缩/解压缩功能的类型和相应的第二存储器的压缩/解压缩功能的类型 设备是一样的 从第一存储装置读取压缩数据而不对第一逻辑卷内的数据进行解压缩，并且将读取的压缩数据写入第二存储装置，该第二存储装置与第二RAID组中的RAID中的相同位置作为 该第一存储设备的RAID中的位置。

公开(公告)号：US20130311854A1

公开(公告)日：2013-11-21

申请号：US13512804

申请日：2012-05-18

申请人： Takashi Tsunehiro ,  Akifumi Suzuki ,  Junji Ogawa

发明人： Takashi Tsunehiro ,  Akifumi Suzuki ,  Junji Ogawa

IPC分类号： G11C29/04 ,  G06F11/16

CPC分类号： G06F11/1068 ,  G11C2029/0411

摘要： A memory controller adds the redundant information that is used to correct an error for each of data of a predetermined length and stores the data into the nonvolatile memory in the case in which data is written to the nonvolatile memory, the memory controller reads data and the redundant information that has been added to the data from the nonvolatile memory in the case in which data is read from the nonvolatile memory, and the memory controller corrects an error based on the redundant information in the case in which the data includes an error. The memory controller stores data that is in a basic unit that is a unit of an error correction configured by the data of a predetermined length and the redundant information that is added to the data of a predetermined length into a plurality of predetermined pages in a dispersed manner.

摘要翻译： 存储器控制器添加用于校正每个预定长度的数据的错误的冗余信息，并且在将数据写入非易失性存储器的情况下将数据存储到非易失性存储器中，存储器控制器读取数据，并且 在从非易失性存储器读取数据的情况下已经添加到来自非易失性存储器的数据的冗余信息，并且存储器控制器在数据包括错误的情况下基于冗余信息来校正错误。 存储器控制器将以预定长度的数据构成的纠错单元的单位的基本单元和附加到预定长度的数据的冗余信息存储到分散的多个预定页面中的数据 方式。

公开(公告)号：US20130151770A1

公开(公告)日：2013-06-13

申请号：US13379186

申请日：2011-12-08

申请人： Junichi Hara ,  Junji Ogawa

发明人： Junichi Hara ,  Junji Ogawa

IPC分类号： G06F12/08

CPC分类号： G06F3/065 ,  G06F3/0626 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0685 ,  G06F3/0689 ,  G06F11/1076 ,  G06F2212/401

摘要： A first storage system comprises a first RAID group comprising multiple first storage devices, which constitute the basis of a first logical volume. A second storage system comprises a second RAID group comprising multiple second storage devices, which constitute the basis of a second logical volume. The RAID configuration of the first RAID group and the RAID configuration of the second RAID group are the same, and the type of a compression/decompression function of the respective first storage devices and the type of a compression/decompression function of the respective second storage devices are the same. Compressed data is read from a first storage device without being decompressed with respect to the data inside a first logical volume, and the read compressed data is written to a second storage device, which is in the same location in RAID in the second RAID group as the location in RAID of this first storage device.

摘要翻译： 第一存储系统包括构成第一逻辑卷的基础的多个第一存储设备的第一RAID组。 第二存储系统包括构成第二逻辑卷的基础的多个第二存储设备的第二RAID组。 第一RAID组的RAID配置和第二RAID组的RAID配置是相同的，并且相应的第一存储设备的压缩/解压缩功能的类型和相应的第二存储器的压缩/解压缩功能的类型 设备是一样的 从第一存储装置读取压缩数据而不对第一逻辑卷内的数据进行解压缩，并且将读取的压缩数据写入第二存储装置，该第二存储装置与第二RAID组中的RAID中的相同位置作为 该第一存储设备的RAID中的位置。

公开(公告)号：US08387063B2

公开(公告)日：2013-02-26

申请号：US11598664

申请日：2006-11-14

申请人： Hideyuki Koseki ,  Junji Ogawa

发明人： Hideyuki Koseki ,  Junji Ogawa

IPC分类号： G06F9/46

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0689 ,  G06F11/3433 ,  G06F2201/81 ,  G06F2206/1012

摘要： This storage apparatus having a plurality of physical devices for balancing and retaining data sent from a host computer and parity of the data for each prescribed unit includes a load ratio calculation unit for calculating a load ratio of the plurality of physical devices, a load ratio determination unit for determining whether the load ratio of the physical devices calculated with the load ratio calculation unit exceeds a prescribed threshold value, a command ratio determination unit for determining whether a command ratio of either a write command or a read command issued from the host computer exceeds a prescribed threshold value when the load ratio determination unit determines that the load ratio of the physical device exceeds a prescribed threshold value, and a change unit for changing the data and the parity among the plurality of physical devices when the command ratio determination unit determines that the command ratio exceeds a prescribed threshold value.

摘要翻译： 具有用于平衡和保留从主计算机发送的数据的多个物理装置的该存储装置以及用于每个规定单元的数据的奇偶校验包括负载比率计算单元，用于计算多个物理装置的负载比，负载比确定 单元，用于确定由所述负载比计算单元计算的所述物理设备的负载比是否超过规定的阈值;命令比率确定单元，用于确定从所述主计算机发出的写入命令或读取命令的命令比是否超过 当所述负载比确定单元确定所述物理设备的负载比超过规定阈值时的规定阈值;以及改变单元，用于当所述指令比率确定单元确定所述多个物理设备之间时，改变所述多个物理设备之间的数据和奇偶校验 指令比例超过规定的阈值。