公开(公告)号：US20130093481A1

公开(公告)日：2013-04-18

申请号：US13275367

申请日：2011-10-18

Applicant: John S. Austin ,  Kai D. Feng ,  Shiu Chung Ho ,  Zhenrong Jin

Inventor： John S. Austin ,  Kai D. Feng ,  Shiu Chung Ho ,  Zhenrong Jin

IPC: H03L7/08

CPC classification number: H03L7/183 ,  H03K23/54

Abstract: A phase lock loop (PLL) includes a PLL feedback circuit having a feedback divider. The feedback divider has a first dynamic latch, a first logic circuit, and a plurality of serially connected dynamic latches. Each of the serially connected dynamic latches receives and forwards additional data signals to subsequent ones of the serially connected dynamic latches in series. The second-to-last dynamic latch in the series outputs a fourth data signal to a last dynamic latch in the series. The last dynamic latch receives the fourth data signal and outputs a fifth data signal. A first feedback loop receives the fourth data signal from the second-to-last dynamic latch and the fifth data signal from the last dynamic latch. The first feedback loop comprises a NAND circuit that combines the fourth and fifth data signals and the first feedback loop outputs the first feedback signal.

Abstract translation: 锁相环（PLL）包括具有反馈分压器的PLL反馈电路。 反馈分压器具有第一动态锁存器，第一逻辑电路和多个串联连接的动态锁存器。 每个串行连接的动态锁存器将附加的数据信号接收并串行连接到后续串行的动态锁存器。 该系列中的第二个到最后一个动态锁存器将第四个数据信号输出到该系列中的最后一个动态锁存器。 最后的动态锁存器接收第四数据信号并输出​​第五数据信号。 第一反馈回路从第二到最后动态锁存器接收第四数据信号，并从最后一个动态锁存器接收第五数据信号。 第一反馈环路包括组合第四和第五数据信号的NAND电路，第一反馈环路输出第一反馈信号。

公开(公告)号：US08416121B2

公开(公告)日：2013-04-09

申请号：US12963314

申请日：2010-12-08

Applicant: Howard H. Chen ,  Kai D. Feng ,  Duixian Liu

Inventor： Howard H. Chen ,  Kai D. Feng ,  Duixian Liu

IPC: G01S7/28

CPC classification number: G01S13/34 ,  G01S13/584 ,  G01S13/931 ,  G01S2007/358

Abstract: A frequency modulation continuous wave (FMCW) system includes a first memory receiving a clock signal and storing voltage digital values of I FMCW signals, a second memory receiving the clock signal and storing the voltage digital values of the Q FMCW signals, a first digital-to-analog converter (DAC) connected to the first memory and receiving the clock signal for converting the voltage digital values of the I FMCW signal to a first analog voltage, a second digital-to-analog converter (DAC) connected to the second memory and receiving the clock signal for converting the voltage digital values of the Q FMCW signal to a second analog voltage, an I low-pass filter connected to the first DAC smoothing the I FMCW signal and a Q low-pass filter connected to the second DAC smoothing the Q FMCW signal.

Abstract translation: 频率调制连续波（FMCW）系统包括接收时钟信号并存储I FMCW信号的电压数字值的第一存储器，接收时钟信号并存储Q FMCW信号的电压数字值的第二存储器，第一数字 - 模拟转换器（DAC），连接到第一存储器并且接收用于将I FMCW信号的电压数字值转换为第一模拟电压的时钟信号;连接到第二存储器的第二数模转换器（DAC） 并接收用于将Q FMCW信号的电压数字值转换为第二模拟电压的时钟信号，连接到第一DAC的I低通滤波器平滑I FMCW信号和连接到第二DAC的Q低通滤波器 平滑Q FMCW信号。

公开(公告)号：US20120256678A1

公开(公告)日：2012-10-11

申请号：US13082434

申请日：2011-04-08

Applicant: Pinping Sun ,  Kai D. Feng ,  Essam Mina

Inventor： Pinping Sun ,  Kai D. Feng ,  Essam Mina

IPC: H03K17/687

CPC classification number: H03K17/693 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/78 ,  H03K17/6221 ,  H03K2017/066 ,  H03K2217/0018

Abstract: A single pole double throw (SPDT) semiconductor switch includes a series connection of a first transmitter-side transistor and a first reception-side transistor between a transmitter node and a reception node. Each of the two first transistors is provided with a gate-side variable impedance circuit, which provides a variable impedance connection between a complementary pair of gate control signals. Further, the body of each first transistor can be connected to a body bias control signal through a body-side variable impedance circuit. In addition, the transmitter node is connected to electrical ground through a second transmitter-side transistor, and the reception node is connected to electrical ground through a second reception-side transistor. Each of the second transistors can have a body bias that is tied to the body bias control signals for the first transistors so that switched-off transistors provide enhanced electrical isolation.

Abstract translation: 单极双掷（SPDT）半导体开关包括在发送器节点和接收节点之间的第一发送器侧晶体管和第一接收侧晶体管的串联连接。 两个第一晶体管中的每一个设置有栅极侧可变阻抗电路，其在互补的一对栅极控制信号之间提供可变阻抗连接。 此外，每个第一晶体管的主体可以通过体侧可变阻抗电路连接到体偏置控制信号。 此外，发射机节点通过第二发射机侧晶体管连接到电接地，并且接收节点通过第二接收侧晶体管连接到电接地。 每个第二晶体管可以具有连接到第一晶体管的体偏置控制信号的体偏置，使得关断晶体管提供增强的电隔离。

公开(公告)号：US20120175612A1

公开(公告)日：2012-07-12

申请号：US13423823

申请日：2012-03-19

Applicant: Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

Inventor： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H01L23/48

CPC classification number: H01L22/34 ,  H01L21/76898

Abstract: A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.

Abstract translation: 半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。

公开(公告)号：US20120132992A1

公开(公告)日：2012-05-31

申请号：US13367646

申请日：2012-02-07

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

IPC: H01L27/12

CPC classification number: H01L27/088 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/1207

Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

Abstract translation: 第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。 第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。 在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。 在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。 第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。 还提供了用于半导体结构的设计结构。

公开(公告)号：US20120056667A1

公开(公告)日：2012-03-08

申请号：US12877159

申请日：2010-09-08

Applicant: Kai D. Feng ,  Jong-Ru Guo ,  Ping-Chuan Wang ,  Zhijian Yang

Inventor： Kai D. Feng ,  Jong-Ru Guo ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H03K5/00

CPC classification number: H03K19/00369

Abstract: An embedded decoupling capacitor wearout monitor for power transmission line, which can be integrated and fabricated in any standard CMOS or BiCMOS circuits. The embedded noise monitor is employed to detect the degraded capacitor and disable it from further operation, which will extend the operation lifetime of the circuit system and prevent subsequent catastrophic failure as a result of hard-breakdown (or capacitor short). In one aspect, the monitor circuit and method detects early degradation signal before catastrophic decoupling capacitor failure and, further can pin-point a degraded decoupling capacitor and disable it, avoiding impact from decoupling capacitor breakdown failure. The monitor circuit and method provides for decoupling capacitor redundancy and includes an embedded and self-diagnostic circuit for functionality and reliability.

Abstract translation: 用于输电线路的嵌入式去耦电容器损耗监测器，可以在任何标准CMOS或BiCMOS电路中集成和制造。 嵌入式噪声监测器用于检测劣化的电容器，并禁止其进一步操作，这将延长电路系统的工作寿命，并防止由于硬击穿（或电容器短路）引起的灾难性故障。 在一个方面，监测电路和方法在灾难性去耦电容器故障之前检测早期劣化信号，并且还可以对劣化的去耦电容进行引脚定位并使其失效，避免去耦电容器击穿故障的影响。 监控电路和方法提供了去耦电容冗余，并且包括用于功能和可靠性的嵌入式和自诊断电路。

公开(公告)号：US08125013B2

公开(公告)日：2012-02-28

申请号：US12191385

申请日：2008-08-14

Applicant: David S. Collins ,  Kai D. Feng ,  Zhong-Xiang Ile ,  Peter J. Lindgren ,  Robert M. Rassel

Inventor： David S. Collins ,  Kai D. Feng ,  Zhong-Xiang Ile ,  Peter J. Lindgren ,  Robert M. Rassel

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L29/66181 ,  H01L29/945

Abstract: A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench.

Abstract translation: 半导体结构和设计结构至少包括布置在衬底中的具有不同深度的第一沟槽和第二沟槽，布置在第一沟槽中的电容器和布置在第二沟槽中的通孔。

公开(公告)号：US20110102005A1

公开(公告)日：2011-05-05

申请号：US12610683

申请日：2009-11-02

Applicant: Kai D. Feng ,  Thomas J. Fleischman ,  Ping-Chuan Wang ,  Xiaojin Wei ,  Zhijian Yang

Inventor： Kai D. Feng ,  Thomas J. Fleischman ,  Ping-Chuan Wang ,  Xiaojin Wei ,  Zhijian Yang

IPC: G01R31/26 ,  G01R31/3187

CPC classification number: G01R31/2856 ,  G01R31/2875

Abstract: An accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. A method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold.

Abstract translation: 嵌入在半导体芯片上的加速故障指示器包括绝缘区域; 位于绝缘区域内的电路; 位于所述绝缘区域内的加热元件，所述加热元件构造成将所述电路加热至高于所述半导体芯片的工作温度的温度; 以及可靠性监视器，其被配置为监视所述电路的劣化，并且还被配置为在所述电路的劣化超过预定阈值的情况下触发警报。 一种操作嵌入在半导体芯片上的加速故障指示器的方法包括确定半导体芯片的工作温度; 将位于加速故障指示器的绝缘区域内的电路加热到高于所确定的工作温度的温度; 监控电路退化; 并且在电路的劣化超过预定阈值的情况下触发报警。

公开(公告)号：US20110019321A1

公开(公告)日：2011-01-27

申请号：US12508665

申请日：2009-07-24

Applicant: Howard H. Chen ,  Kai D. Feng ,  Louis L. Hsu ,  Seongwon Kim

Inventor： Howard H. Chen ,  Kai D. Feng ,  Louis L. Hsu ,  Seongwon Kim

IPC: G01R27/26 ,  H02H3/00

CPC classification number: G01R31/024 ,  G01R31/028

Abstract: A high-density deep trench capacitor array with a plurality of leakage sensors and switch devices. Each capacitor array further comprises a plurality of sub-arrays, wherein the leakage in each sub-array is independently controlled by a sensor and switch unit. The leakage sensor comprises a current mirror, a transimpedance amplifier, a voltage comparator, and a timer. If excessive leakage current is detected, the switch unit will automatically disconnect the leaky capacitor module to reduce stand-by power and improve yield. An optional solid-state resistor can be formed on top of the deep trench capacitor array to increase the temperature and speed up the leakage screening process.

Abstract translation: 一种高密度深沟槽电容阵列，具有多个漏电传感器和开关器件。 每个电容器阵列还包括多个子阵列，其中每个子阵列中的泄漏由传感器和开关单元独立地控制。 泄漏传感器包括电流镜，跨阻放大器，电压比较器和定时器。 如果检测到过大的漏电流，开关单元将自动断开泄漏电容器模块，以降低待机功率并提高产量。 可以在深沟槽电容器阵列的顶部形成可选的固态电阻器，以增加温度并加快泄漏检测过程。

公开(公告)号：US20110018575A1

公开(公告)日：2011-01-27

申请号：US12508111

申请日：2009-07-23

Applicant: Fen Chen ,  Kai D. Feng ,  Zhong-Xiang He

Inventor： Fen Chen ,  Kai D. Feng ,  Zhong-Xiang He

IPC: G01R31/26 ,  G01R31/02

CPC classification number: G01R31/2621 ,  G01R31/2855 ,  G01R31/2894

Abstract: The present invention provides a method. The method includes operating a plurality of field-effect-transistors (FETs) under a first operation condition; reversing an operation direction for at least one of the plurality of FETs for a brief period of time; measuring a second operation condition of the one of the plurality of FETs during the brief period of time; computing a difference between the second operation condition and a reference operation condition; and providing a reliability indicator based upon the difference between the second and the reference operation conditions, wherein the plurality of FETs are employed in a single integrated circuit (IC).

Abstract translation: 本发明提供一种方法。 该方法包括在第一操作条件下操作多个场效应晶体管（FET）; 短时间内反转多个FET中的至少一个的操作方向; 在短时间内测量所述多个FET中的一个的第二操作条件; 计算第二操作条件和参考操作条件之间的差; 以及基于所述第二参考操作条件和所述参考操作条件之间的差异提供可靠性指示器，其中所述多个FET用于单个集成电路（IC）。