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公开(公告)号：US08698228B2
公开(公告)日：2014-04-15
申请号：US12886202
申请日：2010-09-20
IPC分类号： H01L29/792
CPC分类号： H01L27/101 , B82Y10/00 , G11B5/743 , G11B9/04 , G11B9/1472 , G11B9/149 , G11C11/22 , G11C13/0007 , G11C2213/56 , G11C2213/71 , G11C2213/77 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1625 , H01L45/1675
摘要： According to one embodiment, a non-volatile memory device includes a stacked structure and a voltage application portion. The stacked structure includes a memory portion, and an electrode stacked with the memory portion and having a surface having a portion facing the memory portion. The voltage application portion applies a voltage to the memory portion to cause a change in a resistance in the memory portion to store information. The surface includes a first region and a second region. The first region contains at least one of a metallic element, Si, Ga, and As. The first region is conductive. The second region contains at least one of the metallic element, Si, Ga, and As, and has a content ratio of nonmetallic element higher than a content ratio of nonmetallic element in the first region. At least one of the first region and the second region has an anisotropic shape on the surface.
摘要翻译： 根据一个实施例，非易失性存储器件包括堆叠结构和电压施加部分。 堆叠结构包括存储部分和与存储器部分堆叠并具有面向存储部分的部分的表面的电极。 电压施加部分向存储器部分施加电压以引起存储器部分中的电阻的变化以存储信息。 表面包括第一区域和第二区域。 第一区域包含金属元素Si，Ga和As中的至少一种。 第一个区域是导电的。 第二区域包含金属元素Si，Ga和As中的至少一种，并且具有高于第一区域中的非金属元素的含量比的非金属元素的含量比。 第一区域和第二区域中的至少一个在表面上具有各向异性的形状。
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公开(公告)号：US08665634B2
公开(公告)日：2014-03-04
申请号：US13600448
申请日：2012-08-31
CPC分类号： G11C13/0002 , G11C11/1673 , G11C11/419 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/72
摘要： A memory cell array includes memory cells disposed at intersections of first lines and second lines, and each having a rectifying element and a variable resistance element connected in series. A control circuit, when performing an operation to change retained data, applies a first voltage to a selected first line and applies a second voltage to a selected second line; furthermore, applies a third voltage to a non-selected first line; and, moreover, applies a fourth voltage larger than the third voltage to a non-selected second line. An absolute value of a difference between the third voltage and the fourth voltage is set smaller than an absolute value of a difference between the first voltage and the second voltage by an amount of an offset voltage. A value of the offset voltage increases as the absolute value of the difference between the first and second voltages increases.
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公开(公告)号：US20130229852A1
公开(公告)日：2013-09-05
申请号：US13599265
申请日：2012-08-30
申请人： Hiroshi KANNO , Yoichi Minemura , Mizuki Kaneko , Tomonori Kurosawa , Takafumi Shimotori , Takayuki Tsukamoto
发明人： Hiroshi KANNO , Yoichi Minemura , Mizuki Kaneko , Tomonori Kurosawa , Takafumi Shimotori , Takayuki Tsukamoto
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/72
摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of memory cells, a plurality of wires, and a control circuit. The control circuit allows a first current to change a state to flow on a selected cell by applying a first potential difference between a pair of wires that sandwich the selected cell selected from the plurality of memory cells with respect to the semiconductor substrate vertically, and allows a second current lower than the first current to flow on an non-selected cell in the same direction as the direction of the first current by applying a second potential difference between a pair of wires that sandwich the non-selected cell connected to a wire shared with the selected cell on a different layer from the selected cell.
摘要翻译： 根据一个实施例，半导体存储器件包括半导体衬底，多个存储单元，多根导线和控制电路。 控制电路允许第一电流通过在相对于半导体衬底垂直地夹持从多个存储单元中选择的所选择的单元的一对导线之间施加第一电位差来改变选定单元上的状态，并允许 低于第一电流的第二电流，在与所述第一电流的方向相同的方向上在未选择的单元上流动，通过在连接到共享的线的未选择的单元之间施加一对导线之间的第二电位差 所选单元格与选定单元格不同的图层。
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公开(公告)号：US20130229850A1
公开(公告)日：2013-09-05
申请号：US13597773
申请日：2012-08-29
申请人： Mizuki Kaneko , Tomonori Kurosawa , Yoichi Minemura , Hiroshi Kanno , Takafumi Shimotori , Takayuki Tsukamoto
发明人： Mizuki Kaneko , Tomonori Kurosawa , Yoichi Minemura , Hiroshi Kanno , Takafumi Shimotori , Takayuki Tsukamoto
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C2213/72
摘要： A semiconductor storage device includes a memory cell array, and a control circuit. The memory cell array has memory cells including variable resistive elements disposed at intersections of a plurality of first lines and a plurality of second lines. The control circuit performs a set pulse applying operation, and a cure pulse applying operation. The set pulse applying operation applies a set pulse to a variable resistive element so as to cause the variable resistive element to transition from a high resistance state to a low resistance state. The cure pulse applying operation applies a cure pulse to the variable resistive element. The cure pulse has a polarity that is opposite of a polarity of the set pulse, and is larger than the set pulse.
摘要翻译： 半导体存储装置包括存储单元阵列和控制电路。 存储单元阵列具有包括设置在多个第一线和多条第二线的交叉处的可变电阻元件的存储单元。 控制电路执行设定脉冲施加操作和固化脉冲施加操作。 设置脉冲施加操作将设定脉冲施加到可变电阻元件，以使可变电阻元件从高电阻状态转变到低电阻状态。 固化脉冲施加操作对可变电阻元件施加固化脉冲。 固化脉冲具有与设定脉冲的极性相反的极性，并且大于设定脉冲。
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75.发明授权Non-volatile semiconductor memory device including memory cells with a variable resistor 有权包括具有可变电阻器的存储单元的非易失性半导体存储器件公开(公告)号：US08391048B2
公开(公告)日：2013-03-05
申请号：US12846198
申请日：2010-07-29
IPC分类号： G11C11/00
CPC分类号： G11C13/0061 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C13/0097 , G11C2013/0092
摘要： A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.
摘要翻译： 根据本发明的实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元，并且每个由可变电阻器形成，其以非易失性方式存储电阻值作为数据。 根据本发明的实施例的一个方面的非易失性半导体存储器件还包括一个控制器，用于选择给定的一个存储单元，产生用于擦除数据的擦除脉冲，并将擦除脉冲提供给 选择的存储单元。 擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。
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公开(公告)号：US08320157B2
公开(公告)日：2012-11-27
申请号：US12876637
申请日：2010-09-07
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0097 , G11C2213/13 , G11C2213/34 , G11C2213/72
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of first wirings, a plurality of second wirings intersecting the plurality of first wirings, and a plurality of memory cells provided at the intersections of the plurality of first and second wirings and each including a non-ohmic element and a variable resistance element connected in series. The control circuit selects one of the plurality of memory cells, generates an erasing pulse for erasing data from the selected memory cell, and supplies the erasing pulse to the selected memory cell. The control circuit executes data erase by applying a voltage of the erasing pulse to the non-ohmic element in the reverse bias direction.
摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制电路。 存储单元阵列包括多个第一布线，与多条第一布线相交的多条第二布线，以及多个存储单元，设置在多个第一布线和第二布线的交点处，每个包括非欧姆元件和 串联连接的可变电阻元件。 控制电路选择多个存储单元中的一个，产生用于从所选存储单元擦除数据的擦除脉冲，并将擦除脉冲提供给所选存储单元。 控制电路通过在反向偏置方向上向非欧姆元件施加擦除脉冲的电压来执行数据擦除。
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公开(公告)号：US08274822B2
公开(公告)日：2012-09-25
申请号：US13018757
申请日：2011-02-01
申请人： Takayuki Tsukamoto , Yoichi Minemura , Natsuki Kikuchi , Mitsuru Sato , Hiroshi Kanno , Takafumi Shimotori
发明人： Takayuki Tsukamoto , Yoichi Minemura , Natsuki Kikuchi , Mitsuru Sato , Hiroshi Kanno , Takafumi Shimotori
IPC分类号： G11C11/00
CPC分类号： H01L45/04 , G11C5/147 , G11C13/0007 , G11C13/0038 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/72 , H01L45/145
摘要： According to one embodiment, a nonvolatile memory device includes a memory unit and a control unit. The memory unit includes first and second interconnects, and a memory cell. The second interconnect is non-parallel to the first interconnect. The memory cell includes a resistance change layer provided at an intersection between the first and second interconnects. The control unit is connected to the first and second interconnects to supply voltage and current to the resistance change layer. The control unit increases an upper limit of a current supplied to the first interconnect based on a change of a potential of the first interconnect when applying a set operation voltage to the first interconnect in a set operation of changing the resistance change layer from a first state with a first resistance value to a second state with a second resistance value being less than the first resistance value.
摘要翻译： 根据一个实施例，非易失性存储器件包括存储器单元和控制单元。 存储单元包括第一和第二互连以及存储单元。 第二互连与第一互连不平行。 存储单元包括设置在第一和第二互连之间的交叉点处的电阻变化层。 控制单元连接到第一和第二互连以向电阻变化层提供电压和电流。 控制单元在将电阻变化层从第一状态变化的设定动作中，基于第一配线的电位的变化来增大提供给第一配线的电流的上限， 具有第一电阻值到第二状态，其中第二电阻值小于第一电阻值。
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公开(公告)号：US20120012807A1
公开(公告)日：2012-01-19
申请号：US13182095
申请日：2011-07-13
申请人： Takeshi YAMAGUCHI , Hirofumi Inoue , Reika Ichihara , Takayuki Tsukamoto , Takashi Shigeoka , Katsuyuki Sekine , Shinya Aoki
发明人： Takeshi YAMAGUCHI , Hirofumi Inoue , Reika Ichihara , Takayuki Tsukamoto , Takashi Shigeoka , Katsuyuki Sekine , Shinya Aoki
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , H01L27/2409 , H01L45/08 , H01L45/1233
摘要： A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.
摘要翻译： 实施例中的半导体存储器件包括存储单元，每个存储单元设置在第一线和第二线之间，并且具有串联连接的可变电阻元件和开关元件。 可变电阻元件包括可变电阻层，其被配置为在低电阻状态和高电阻状态之间改变其电阻值。 可变电阻层由过渡金属氧化物构成。 构成过渡金属氧化物的过渡金属和氧的比例沿着从第一线指向第二线的第一方向在1:1和1:2之间变化。
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公开(公告)号：US20110235401A1
公开(公告)日：2011-09-29
申请号：US13052214
申请日：2011-03-21
CPC分类号： H01L27/24 , G11C8/08 , G11C13/0007 , G11C13/0023 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , H01L27/1021
摘要： A nonvolatile semiconductor memory device according to an embodiment herein includes a memory cell array. The memory cell array includes memory cells each provided between a first line and a second line and each including a variable resistor. A control circuit applies through the first and second lines a voltage necessary for a forming operation of the memory cell. A current limiting circuit limits a value of a current flowing across the memory cell during the forming operation to a certain limit value. The control circuit repeats an operation of applying the voltage by setting the limit value to a certain value and an operation of changing the limit value from the certain value, until forming of the memory cell is achieved.
摘要翻译： 根据本文实施例的非易失性半导体存储器件包括存储单元阵列。 存储单元阵列包括各自设置在第一线路和第二线路之间并且各自包括可变电阻器的存储器单元。 控制电路通过第一和第二行施加存储单元的形成操作所需的电压。 电流限制电路将在成形操作期间流过存储器单元的电流的值限制到某一极限值。 控制电路重复通过将极限值设定为一定值来施加电压的操作和从该特定值改变极限值的操作，直到实现存储单元的形成。
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公开(公告)号：US20110216574A1
公开(公告)日：2011-09-08
申请号：US12886931
申请日：2010-09-21
申请人： Reika ICHIHARA , Takayuki Tsukamoto
发明人： Reika ICHIHARA , Takayuki Tsukamoto
IPC分类号： G11C11/00
CPC分类号： G11C11/00 , G11C2013/0083
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.
摘要翻译： 根据实施例的非易失性半导体存储器件包括多个第一，第二线，多个存储单元和控制电路。 多个第二线延伸以与第一线相交。 多个存储单元设置在第一和第二线的交点处，并且每个都包括可变电阻器。 控制电路被配置为控制施加到存储器单元的电压。 控制电路在成形操作期间向可变电阻器施加第一脉冲电压。 此外，控制电路在设定操作期间向可变电阻施加第二脉冲电压，第二脉冲电压具有与第一脉冲电压相反的极性。 此外，控制电路在复位操作期间向可变电阻器施加第三脉冲电压，第三脉冲电压具有与第一脉冲电压相同的极性。
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