利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

586 条记录 (耗时 0.07 秒)

    Overlay-tolerant via mask and reactive ion etch (RIE) technique
    73.
    发明授权
    Overlay-tolerant via mask and reactive ion etch (RIE) technique 有权
    覆盖层通过掩模和反应离子蚀刻（RIE）技术

    公开(公告)号：US09059254B2

    公开(公告)日：2015-06-16

    申请号：US13604660

    申请日：2012-09-06

    申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L21/311

    CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

    摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.

    摘要翻译： 提供了一种方法，其包括首先根据第一掩模蚀刻衬底。 第一蚀刻在衬底中形成第一深度的第一蚀刻特征。 第一蚀刻还在衬底中形成条条开口。 然后可以用填充材料填充条子开口。 可以通过去除第一掩模的一部分来形成第二掩模。 可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。 第二蚀刻将第一蚀刻特征扩展到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。 然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。

    Structure and metallization process for advanced technology nodes
    74.
    发明授权
    Structure and metallization process for advanced technology nodes 有权
    先进技术节点的结构和金属化过程

    公开(公告)号：US08957519B2

    公开(公告)日：2015-02-17

    申请号：US12910075

    申请日：2010-10-22

    申请人： Chih-Chao Yang ,  Hsueh-Chung Chen

    发明人： Chih-Chao Yang ,  Hsueh-Chung Chen

    IPC分类号： H01L23/48 ,  H01L21/321 ,  H01L21/02 ,  H01L21/768

    CPC分类号： H01L21/321 ,  H01L21/02304 ,  H01L21/76852 ,  H01L21/76886

    摘要： The problem of poor adherence of a dielectric coating on a patterned metal structure can be solved by forming an adhesion layer on exposed surfaces of such metal structure prior to deposition of such dielectric. According to an embodiment, the invention provides a method to form a self-aligned adhesion layer on the surface of metal interconnect structure within an integrated circuit by exposing the metal structure to a controlled atmosphere and a flow of nitrogen-containing gas.

    摘要翻译： 可以通过在沉积这种电介质之前在这种金属结构的暴露表面上形成粘合层来解决图案化金属结构上的电介质涂层粘附性差的问题。 根据一个实施例，本发明提供了一种通过将金属结构暴露于受控气氛和含氮气体的流动来在集成电路内的金属互连结构的表面上形成自对准粘附层的方法。

    Borderless interconnect line structure self-aligned to upper and lower level contact vias
    78.
    发明授权
    Borderless interconnect line structure self-aligned to upper and lower level contact vias 有权
    无边界互连线结构自对准到上层和下层接触孔

    公开(公告)号：US08704343B2

    公开(公告)日：2014-04-22

    申请号：US13607677

    申请日：2012-09-08

    申请人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

    发明人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

    IPC分类号： H01L21/44

    CPC分类号： H01L23/528 ,  H01L21/76885 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.

    摘要翻译： 金属层沉积在其上暴露下面的金属通孔的顶表面的平坦表面上。 图案化金属层以形成至少一个金属块，其具有要形成的金属线的水平横截面积和要形成的至少一个上覆的金属通孔。 下面的金属通孔的每个上部凹陷在位于正上方的金属块的区域的外部。 至少一个金属块的上部被光刻地图案化以形成集成线和通孔结构，其包括具有基本上恒定的宽度的金属线和至少一个覆盖的金属通孔，其具有相同的基本上恒定的宽度并且与金属线无边界地对准 。 沉积和平坦化上层电介质材料层，使得至少一个上覆金属通孔的顶表面被暴露。

    Creation of vias and trenches with different depths
    79.
    发明授权
    Creation of vias and trenches with different depths 有权
    创造不同深度的通道和沟渠

    公开(公告)号：US08703604B2

    公开(公告)日：2014-04-22

    申请号：US13415164

    申请日：2012-03-08

    申请人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

    发明人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

    IPC分类号： H01L21/311 ,  H01L21/3065

    CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

    摘要翻译： 本发明的实施例提供了一种创建具有不同长度的通孔和沟槽的方法。 该方法包括在半导体结构的顶部上沉积多个电介质层，多个电介质层被至少一个蚀刻停止层隔开; 通过非选择性蚀刻工艺从所述多个电介质层的顶表面形成多个开口到多个介电层中，其中所述多个开口中的至少一个具有在所述蚀刻步骤层下方的深度; 以及通过选择性蚀刻工艺继续蚀刻多个开口，直到位于蚀刻停止层上方的多个开口的一个或多个开口到达和暴露蚀刻停止层。 也提供了由此制成的半导体结构。

    METHOD TO IMPROVE FINE CU LINE RELIABILITY IN AN INTEGRATED CIRCUIT DEVICE
    80.
    发明申请
    METHOD TO IMPROVE FINE CU LINE RELIABILITY IN AN INTEGRATED CIRCUIT DEVICE 有权
    在集成电路设备中提高精细线路可靠性的方法

    公开(公告)号：US20140048927A1

    公开(公告)日：2014-02-20

    申请号：US13587998

    申请日：2012-08-17

    申请人： Chad M. Burke ,  Baozhen Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    发明人： Chad M. Burke ,  Baozhen Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/76847 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Structure and methods for forming a semiconductor structure. The semiconductor structure includes a plurality of layers comprising at least one copper interconnect layer. The copper interconnect layer provides an electrical conduit between one of physically adjacent layers in the semiconductor structure and an integrated circuit in the semiconductor structure and an electronic device. A plurality of studs is positioned within the at least one copper interconnect layer. The studs are spaced apart by a distance less than or equal to a Blech length of the at least one copper interconnect layer. The Blech length is a length below which damage due to electromigration of metal atoms within the at least one copper interconnect layer does not occur. The plurality of studs comprises copper atom diffusion barriers.

    摘要翻译： 用于形成半导体结构的结构和方法。 半导体结构包括包括至少一个铜互连层的多个层。 铜互连层在半导体结构中的物理相邻层之一和半导体结构中的集成电路和电子器件之间提供电导体。 多个螺柱被定位在所述至少一个铜互连层内。 螺栓间隔开小于或等于至少一个铜互连层的Blech长度的距离。 漂浮长度是低于该值的长度，在该长度之下不会发生由于至少一个铜互连层内的金属原子的电迁移而导致的损伤。 多个螺柱包括铜原子扩散阻挡层。