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    Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
    74.
    发明授权
    Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates 有权
    形成场效应晶体管的方法，形成场效应晶体管栅极的方法，形成集成电路的方法，包括晶体管栅极阵列和门阵列外围的电路，以及形成集成电路的方法，该集成电路包括晶体管栅极阵列，其包括第一栅极和第二接地 隔离门

    公开(公告)号：US07700441B2

    公开(公告)日：2010-04-20

    申请号：US11346914

    申请日：2006-02-02

    申请人： Young Pil Kim ,  Kunal R. Parekh

    发明人： Young Pil Kim ,  Kunal R. Parekh

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823462 ,  H01L21/823456 ,  H01L21/823487 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621

    摘要： The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括形成场效应晶体管的方法，形成场效应晶体管栅极的方法，形成集成电路的方法，该集成电路包括晶体管栅极阵列和外围于栅极阵列的电路，以及形成集成电路的方法，该集成电路包括晶体管栅极阵列，其包括第一栅极 和第二接地隔离门。 在一个实施方案中，形成场效应晶体管的方法包括在衬底的半导体材料上形成掩模材料。 通过掩模材料形成沟槽并进入半导体材料。 栅介电材料形成在半导体材料的沟槽内。 栅极材料沉积在掩模材料中的沟槽内并且在半导体材料中的沟槽内沉积在栅极电介质材料上。 形成源/漏区。 考虑了其他方面和实现。

    Methods of forming memory circuitry
    76.
    发明授权
    Methods of forming memory circuitry 有权
    形成存储器电路的方法

    公开(公告)号：US07462534B2

    公开(公告)日：2008-12-09

    申请号：US11196051

    申请日：2005-08-02

    申请人： Kunal R. Parekh ,  Suraj Mathew ,  Steve Cole

    发明人： Kunal R. Parekh ,  Suraj Mathew ,  Steve Cole

    IPC分类号： H01L21/8244

    CPC分类号： H01L29/6656 ,  H01L27/10882 ,  H01L27/10891 ,  H01L27/10894

    摘要： The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a peripheral circuitry area. The memory array circuitry area comprises transistor gate lines having a first minimum line spacing. The peripheral circuitry area comprises transistor gate lines having a second minimum line spacing which is greater than the first minimum line spacing. Anisotropically etched insulative sidewall spacers are formed over opposing sidewalls of individual of said transistor gate lines within the peripheral circuitry area prior to forming anisotropically etched insulative sidewall spacers over opposing sidewalls of individual of said transistor gate lines within the memory array area. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括形成存储器电路的方法。 在一个实现中，提供了具有存储器阵列电路区域和外围电路区域的衬底。 存储器阵列电路区域包括具有第一最小线间距的晶体管栅极线。 外围电路区域包括具有大于第一最小线间距的第二最小线间距的晶体管栅极线。 在存储器阵列区域内的所述晶体管栅极线的单独的相对侧壁上形成各向异性蚀刻的绝缘侧壁间隔物之前，在外围电路区域内的所述晶体管栅极线的单独的相对侧壁上形成各向异性蚀刻的绝缘侧壁间隔物。 考虑了其他方面和实现。

    Gated field effect devices
    78.
    发明授权
    Gated field effect devices 失效
    门控场效应器件

    公开(公告)号：US07442977B2

    公开(公告)日：2008-10-28

    申请号：US11253461

    申请日：2005-10-19

    申请人： Cem Basceri ,  H. Montgomery Manning ,  Gurtej S. Sandhu ,  Kunal R. Parekh

    发明人： Cem Basceri ,  H. Montgomery Manning ,  Gurtej S. Sandhu ,  Kunal R. Parekh

    IPC分类号： H01L27/108

    CPC分类号： H01L29/4983 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/517

    摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括门控场效应器件，以及形成门控场效应器件的方法。 在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。 在源极/漏极区域之间的沟道区域附近接收栅极。 栅极在源极/漏极区之间具有栅极宽度。 栅极电介质被接收在沟道区域和栅极之间。 栅极电介质沿着栅极的宽度具有至少两个不同的区域。 不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。 考虑了其他方面和实现。

    Dopant barrier for doped glass in memory devices
    79.
    发明授权
    Dopant barrier for doped glass in memory devices 有权
    存储器件中掺杂玻璃的掺杂阻挡层

    公开(公告)号：US07411255B2

    公开(公告)日：2008-08-12

    申请号：US11003138

    申请日：2004-12-03

    申请人： Kunal R. Parekh ,  Gurtej Singh Sandhu

    发明人： Kunal R. Parekh ,  Gurtej Singh Sandhu

    IPC分类号： H01L29/76

    CPC分类号： H01L21/76897 ,  H01L21/28247 ,  H01L21/3003 ,  H01L21/76832

    摘要： A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface structures, while adequately preventing dopants in doped glass layer from diffusing out of the doped glass layer to the surface structures and the substrate. Further, heavy water can be used during the formation of the alumina so that deuterium may be accomplished near the interface of surface structures and the substrate to enhance the performance of the device.

    摘要翻译： 半导体器件具有在掺杂的玻璃层和形成在衬底上的表面结构之间形成的扩散阻挡层。 扩散阻挡层包括氧化铝和任选的氮化物，并且具有满足表面结构之间的间隙的高纵横比的层厚度，同时充分防止掺杂的玻璃层中的掺杂剂从掺杂的玻璃层扩散到表面结构，并且 基质。 此外，在形成氧化铝期间可以使用重水，使得可以在表面结构和基底的界面附近实现氘，以增强器件的性能。

    Methods of forming recessed access devices associated with semiconductor constructions
    80.
    发明授权
    Methods of forming recessed access devices associated with semiconductor constructions 有权
    形成与半导体结构相关联的凹陷接入设备的方法

    公开(公告)号：US07384849B2

    公开(公告)日：2008-06-10

    申请号：US11090529

    申请日：2005-03-25

    申请人： Kunal R. Parekh ,  Suraj Mathew ,  Jigish D. Trivedi ,  John K. Zahurak ,  Sanh D. Tang

    发明人： Kunal R. Parekh ,  Suraj Mathew ,  Jigish D. Trivedi ,  John K. Zahurak ,  Sanh D. Tang

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10876 ,  H01L27/10823

    摘要： The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.

    摘要翻译： 本发明包括形成凹入进入装置的方法。 提供基板以在其中具有凹入的接入装置沟槽。 一对凹进的接入设备沟槽彼此相邻。 导电材料形成在凹进的存取装置沟槽内，源极/漏极区域靠近导电材料形成。 导电材料和源极/漏极区域一起被并入一对相邻的凹进入器件中。 在凹陷的访问设备沟槽形成在衬底内之后，在相邻的凹进的访问设备之间形成隔离区沟槽，并且填充有电绝缘材料以形成沟槽隔离区域。