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    Dopant barrier for doped glass in memory devices
    1.
    发明授权
    Dopant barrier for doped glass in memory devices 有权
    存储器件中掺杂玻璃的掺杂阻挡层

    公开(公告)号：US07411255B2

    公开(公告)日：2008-08-12

    申请号：US11003138

    申请日：2004-12-03

    申请人： Kunal R. Parekh ,  Gurtej Singh Sandhu

    发明人： Kunal R. Parekh ,  Gurtej Singh Sandhu

    IPC分类号： H01L29/76

    CPC分类号： H01L21/76897 ,  H01L21/28247 ,  H01L21/3003 ,  H01L21/76832

    摘要： A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface structures, while adequately preventing dopants in doped glass layer from diffusing out of the doped glass layer to the surface structures and the substrate. Further, heavy water can be used during the formation of the alumina so that deuterium may be accomplished near the interface of surface structures and the substrate to enhance the performance of the device.

    摘要翻译： 半导体器件具有在掺杂的玻璃层和形成在衬底上的表面结构之间形成的扩散阻挡层。 扩散阻挡层包括氧化铝和任选的氮化物，并且具有满足表面结构之间的间隙的高纵横比的层厚度，同时充分防止掺杂的玻璃层中的掺杂剂从掺杂的玻璃层扩散到表面结构，并且 基质。 此外，在形成氧化铝期间可以使用重水，使得可以在表面结构和基底的界面附近实现氘，以增强器件的性能。

    Dopant barrier for doped glass in memory devices
    4.
    发明授权
    Dopant barrier for doped glass in memory devices 有权
    存储器件中掺杂玻璃的掺杂阻挡层

    公开(公告)号：US07132371B2

    公开(公告)日：2006-11-07

    申请号：US10931591

    申请日：2004-08-31

    申请人： Kunal R. Parekh ,  Gurtej Singh Sandhu

    发明人： Kunal R. Parekh ,  Gurtej Singh Sandhu

    IPC分类号： H01L21/31

    CPC分类号： H01L21/76897 ,  H01L21/28247 ,  H01L21/3003 ,  H01L21/76832

    摘要： A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface structures, while adequately preventing dopants in doped glass layer from diffusing out of the doped glass layer to the surface structures and the substrate. Further, heavy water can be used during the formation of the alumina so that deuterium may be accomplished near the interface of surface structures and the substrate to enhance the performance of the device.

    摘要翻译： 半导体器件具有在掺杂的玻璃层和形成在衬底上的表面结构之间形成的扩散阻挡层。 扩散阻挡层包括氧化铝和任选的氮化物，并且具有满足表面结构之间的间隙的高纵横比的层厚度，同时充分防止掺杂的玻璃层中的掺杂剂从掺杂的玻璃层扩散到表面结构，并且 基质。 此外，在形成氧化铝期间可以使用重水，使得可以在表面结构和基底的界面附近实现氘，以增强器件的性能。

    Dopant barrier for doped glass in memory devices
    6.
    发明授权
    Dopant barrier for doped glass in memory devices 有权

    公开(公告)号：US06833575B2

    公开(公告)日：2004-12-21

    申请号：US10233279

    申请日：2002-08-29

    申请人： Kunal R. Parekh ,  Gurtej Singh Sandhu

    发明人： Kunal R. Parekh ,  Gurtej Singh Sandhu

    IPC分类号： H01L27108

    CPC分类号： H01L21/76897 ,  H01L21/28247 ,  H01L21/3003 ,  H01L21/76832

    摘要： A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface structures, while adequately preventing dopants in doped glass layer from diffusing out of the doped glass layer to the surface structures and the substrate. Further, heavy water can be used during the formation of the alumina so that deuterium may be accomplished near the interface of surface structures and the substrate to enhance the performance of the device.

    Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
    7.
    发明授权
    Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array 有权
    形成非易失性电阻氧化物存储单元的方法和形成非易失性电阻氧化物存储器阵列的方法

    公开(公告)号：US09343665B2

    公开(公告)日：2016-05-17

    申请号：US12166604

    申请日：2008-07-02

    申请人： Nishant Sinha ,  John Smythe ,  Bhaskar Srinivasan ,  Gurtej S. Sandhu ,  Joseph Neil Greeley ,  Kunal R. Parekh

    发明人： Nishant Sinha ,  John Smythe ,  Bhaskar Srinivasan ,  Gurtej S. Sandhu ,  Joseph Neil Greeley ,  Kunal R. Parekh

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/1683 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

    摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.

    摘要翻译： 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 含金属氧化物的材料形成在第一导电电极上。 蚀刻停止材料沉积在包含金属氧化物的材料上。 导电材料沉积在蚀刻停止材料上。 包含所接收的导电材料的存储单元的第二导电电极形成在蚀刻停止材料上。 这样包括通过导电材料蚀刻以相对于蚀刻停止材料停止并且形成非易失性电阻氧化物存储单元，以包括具有包含金属氧化物的材料和其间的蚀刻停止材料的第一和第二导电电极。 考虑其他实现。

    Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
    10.
    发明授权
    Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates 有权
    形成场效应晶体管的方法，形成场效应晶体管栅极的方法，形成集成电路的方法，包括晶体管栅极阵列和门阵列外围的电路，以及形成集成电路的方法，该集成电路包括晶体管栅极阵列，其包括第一栅极和第二接地 隔离门

    公开(公告)号：US07902028B2

    公开(公告)日：2011-03-08

    申请号：US12724589

    申请日：2010-03-16

    申请人： Young Pil Kim ,  Kunal R. Parekh

    发明人： Young Pil Kim ,  Kunal R. Parekh

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823462 ,  H01L21/823456 ,  H01L21/823487 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621

    摘要： The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括形成场效应晶体管的方法，形成场效应晶体管栅极的方法，形成集成电路的方法，该集成电路包括晶体管门阵列和门阵列的外围电路，以及形成集成电路的方法，该集成电路包括晶体管门阵列，其包括第一栅极 和第二接地隔离门。 在一个实施方案中，形成场效应晶体管的方法包括在衬底的半导体材料上形成掩模材料。 通过掩模材料形成沟槽并进入半导体材料。 栅介电材料形成在半导体材料的沟槽内。 栅极材料沉积在掩模材料中的沟槽内并且在半导体材料中的沟槽内沉积在栅极电介质材料上。 形成源/漏区。 考虑了其他方面和实现。