公开(公告)号：US20220139426A1

公开(公告)日：2022-05-05

申请号：US17494606

申请日：2021-10-05

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth

IPC: G11C5/06 ,  G11C5/02

Abstract: Methods, systems, and devices for memory with fine grain architectures are described. An apparatus may include a memory device, a first organic substrate, and a second organic substrate. The first organic substrate may include a plurality of first conductive lines arranged with a first pitch that may power one or more components of the memory device. The second organic substrate may be coupled with the memory device and the first organic substrate. The second organic substrate may include a plurality of second conductive lines arranged with a second pitch smaller than the first pitch and may be configured to route signals between the memory device with a host device.

公开(公告)号：US20220004421A1

公开(公告)日：2022-01-06

申请号：US17479733

申请日：2021-09-20

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Naveh Malihi

IPC: G06F9/455 ,  H04L9/14 ,  G06F12/14

Abstract: Apparatuses and methods related to managing regions of memory are described. Managing regions can include verifying whether an access command is authorized to access a particular region of a memory array, which may have some regions that have rules or restrictions governing access (e.g., so-called “protected regions”). The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the region, then a row of the memory array corresponding to the access command may not be activated.

公开(公告)号：US10936221B2

公开(公告)日：2021-03-02

申请号：US15981708

申请日：2018-05-16

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  James Brian Johnson

IPC: G11C7/10 ,  G06F3/06 ,  H01L23/538 ,  H01L25/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/22 ,  G06F11/10 ,  H01L25/065 ,  H01L23/50 ,  G11C5/02 ,  G11C11/00 ,  H01L23/14 ,  G11C11/4097

Abstract: Techniques are described herein for a reconfigurable memory device that is configurable based on the type of interposer used to couple the memory device with a host device. The reconfigurable memory device may include a plurality components for a plurality of configurations. Various components of the reconfigurable memory die may be activated/deactivated based on what type of interposer is used in the memory device. For example, if a first type of interposer is used (e.g., a high-density interposer), the data channel may be eight data pins wide. In contrast, if second type of interposer is used (e.g., an organic-based interposer), the data channel may be four data pins wide. As such, a reconfigurable memory device may include data pins and related drivers that are inactive in some configurations.

公开(公告)号：US20200350224A1

公开(公告)日：2020-11-05

申请号：US16936639

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L25/00 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18 ,  H01L23/373 ,  H01L23/42

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US20200285498A1

公开(公告)日：2020-09-10

申请号：US16295708

申请日：2019-03-07

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Naveh Malihi

IPC: G06F9/455 ,  H04L9/14 ,  G06F12/14

Abstract: Apparatuses and methods related to managing regions of memory are described. Managing regions can include verifying whether an access command is authorized to access a particular region of a memory array, which may have some regions that have rules or restrictions governing access (e.g., so-called “protected regions”). The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the region, then a row of the memory array corresponding to the access command may not be activated.

公开(公告)号：US10579578B2

公开(公告)日：2020-03-03

申请号：US15981703

申请日：2018-05-16

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth

IPC: G06F13/00 ,  G06F13/42 ,  G06F15/167

Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.

公开(公告)号：US20190385646A1

公开(公告)日：2019-12-19

申请号：US16279590

申请日：2019-02-19

Applicant: Micron Technology, Inc.

Inventor： Joe M. Jeddeloh ,  Brent Keeth

IPC: G11C5/06 ,  G11C5/14 ,  G11C7/10 ,  H01L25/065 ,  G11C5/02

Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.

公开(公告)号：US20190179785A1

公开(公告)日：2019-06-13

申请号：US16058873

申请日：2018-08-08

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Richard C. Murphy ,  Elliott C. Cooper-Balis

IPC: G06F13/28 ,  G06F12/10 ,  H01L25/065 ,  H01L25/18 ,  H01L23/538 ,  G06F13/16

Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.

公开(公告)号：US20190088652A1

公开(公告)日：2019-03-21

申请号：US16183468

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang ,  Suraj J. Mathew ,  Raghunath Singanamalla ,  Vinay Nair ,  Scott J. Derner ,  Michael Amiel Shore ,  Brent Keeth ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/423 ,  G11C11/403 ,  H01L29/78 ,  H01L29/10 ,  H01L27/06 ,  H01L29/08 ,  H01L23/528

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

公开(公告)号：US20190081024A1

公开(公告)日：2019-03-14

申请号：US16190523

申请日：2018-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Adam S. El-Mansouri ,  Fuad Badrieh ,  Brent Keeth

IPC: H01L25/065 ,  G05F1/10

CPC classification number: H01L25/0657 ,  G05F1/10 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541

Abstract: Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. The semiconductor device includes: a substrate on the circuit board, stacked via conductive balls, that receives the first voltage from the power line via the conductive balls; a plurality of dies on the semiconductor device, stacked via bumps, each die including, a first conductive via that receives the first voltage via the bumps; a plurality of pillars between adjacent dies and couple the first conductive vias of the adjacent dies; and a sense node switch circuit that selectively couples one first conductive via of one die among the plurality of dies to the regulator.