公开(公告)号：US20220261363A1

公开(公告)日：2022-08-18

申请号：US17673731

申请日：2022-02-16

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Daniele Balluchi ,  Paolo Amato ,  Danilo Caraccio ,  Marco Sforzin

IPC: G06F13/16

Abstract: Systems, apparatuses, and methods related to a controller for managing multiple types of memory are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics. The central controller portion is configured to cause performance of a memory operation and comprises a cache memory to buffer data associated performance of the memory operation, a security component configured to encrypt the data before storing the data in the first type of memory device or the second type of memory device, and error correction code (ECC) circuitry to ECC encode and ECC decode the data.

公开(公告)号：US11379139B2

公开(公告)日：2022-07-05

申请号：US17020460

申请日：2020-09-14

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Federico Tiziani

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/38 ,  G06F9/50 ,  G11C14/00 ,  G11C13/00

Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

公开(公告)号：US11132311B2

公开(公告)日：2021-09-28

申请号：US16702980

申请日：2019-12-04

Applicant: Micron Technology, Inc.

Inventor： Dionisio Minopoli ,  Gianfranco Ferrante ,  Antonino Caprí ,  Emanuele Confalonieri ,  Daniele Balluchi

IPC: G06F13/16 ,  G06F3/06 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4093 ,  G06F13/42 ,  G06F13/32 ,  G06F13/22 ,  G06F9/38

Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.

公开(公告)号：US10956290B2

公开(公告)日：2021-03-23

申请号：US16214701

申请日：2018-12-10

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

IPC: G06F11/20 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.

公开(公告)号：US20210064261A1

公开(公告)日：2021-03-04

申请号：US17020460

申请日：2020-09-14

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Federico Tiziani

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/38 ,  G06F9/50 ,  G11C14/00

Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

公开(公告)号：US10809942B2

公开(公告)日：2020-10-20

申请号：US15927383

申请日：2018-03-21

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora ,  Roberto Izzi ,  Paolo Amato ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F3/06 ,  G06F12/10

Abstract: An example apparatus comprises a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to cause data associated with a virtual memory location of the host to be selectively transferred to the hybrid memory system responsive to a determination that a main memory of the host experiences threshold amount of resource utilization.

公开(公告)号：US10755751B2

公开(公告)日：2020-08-25

申请号：US16426435

申请日：2019-05-30

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Stefano Ratti ,  Gary G. Lazarowics ,  Stefan Frederik Schippers ,  Stefano Claudio Roseghini ,  Angelo Clemente Scardilla

IPC: G11C16/26 ,  G11C7/04 ,  G01K3/00 ,  G11C16/34 ,  G11C13/00 ,  G06F3/06

Abstract: Apparatuses, methods, and devices that can be utilized to provide temperature-based memory operations are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: determine an operating temperature of the apparatus, determine one of a plurality of designated open blocks of the memory device to write data based on the operating temperature of the apparatus and a size of the data, and write the data in the determined one of the plurality of designated blocks of the memory device.

公开(公告)号：US10534731B2

公开(公告)日：2020-01-14

申请号：US15924917

申请日：2018-03-19

Applicant: Micron Technology, Inc.

Inventor： Dionisio Minopoli ,  Gianfranco Ferrante ,  Antonino Caprí ,  Emanuele Confalonieri ,  Daniele Balluchi

IPC: G06F13/16 ,  G06F3/06 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4093 ,  G06F13/42 ,  G06F13/32 ,  G06F13/22 ,  G06F9/38

Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.

公开(公告)号：US20190294363A1

公开(公告)日：2019-09-26

申请号：US15927383

申请日：2018-03-21

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora ,  Roberto Izzi ,  Paolo Amato ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F3/06 ,  G06F12/10

Abstract: An example apparatus comprises a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to cause data associated with a virtual memory location of the host to be selectively transferred to the hybrid memory system responsive to a determination that a main memory of the host experiences threshold amount of resource utilization.

公开(公告)号：US20190171385A1

公开(公告)日：2019-06-06

申请号：US16201729

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Federico Tiziani

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/38 ,  G06F9/50 ,  G11C14/00

CPC classification number: G06F3/0644 ,  G06F3/0607 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0637 ,  G06F3/0685 ,  G06F9/5077 ,  G06F12/0223 ,  G06F12/0238 ,  G06F12/0246 ,  G06F13/385 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2213/3804 ,  G06F2213/3854 ,  G11C13/0002 ,  G11C13/0004 ,  G11C14/009 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.