公开(公告)号：US12057400B2

公开(公告)日：2024-08-06

申请号：US17395726

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L23/5283 ,  H01L23/53266 ,  H10B41/27 ,  H10B43/27

Abstract: Some embodiments include an integrated assembly having a stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions have first conductive structures, and the proximal regions have second conductive structures. Detectable interfaces are present where the first conductive structures join to the second conductive structures. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12052862B2

公开(公告)日：2024-07-30

申请号：US17549237

申请日：2021-12-13

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Shyam Surthi

IPC: H01L27/11556 ,  G11C5/02 ,  H01L23/538 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  H01L23/5386 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure, a staircase structure, an etch stop material, and insulative material. The stack structure comprises conductive structures, and air gaps vertically alternating with the conductive structures. The staircase structure is within the stack structure and has steps comprising edges of at least some of the conductive structures of the stack structure. The etch stop material continuously extends over the conductive structures and at least partially defines horizontal boundaries of the air gaps. The insulative material overlies the etch stop material. Additional microelectronic devices, memory devices, electronic systems, and methods are also disclosed.

公开(公告)号：US12041779B2

公开(公告)日：2024-07-16

申请号：US17678983

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Kunal Shrotri ,  Matthew Thorum

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230320085A1

公开(公告)日：2023-10-05

申请号：US17710262

申请日：2022-03-31

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11556 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising vertically-alternating insulative tiers and conductive tiers directly above a conductor tier. Channel-material-string constructions of memory-cell strings extend through the insulative and conductive tiers. The channel material of the channel-material-string constructions directly electrically couples with conductor material of the conductor tier. The vertical stack comprising a memory-cell region comprises memory cells. Individual of the insulative tiers in the memory-cell region laterally-outward of the channel-material-string constructions have at least a majority of their insulative matter being void space. The vertical stack comprises an upper region directly above the memory-cell region. The upper region comprises at least two of the conductive tiers and that comprise upper select gates Individual of the insulative tiers in the upper region laterally-outward of the channel-material-string constructions have at least a majority of their insulative matter being solid. Other embodiments, including method, are disclosed.

公开(公告)号：US20230262981A1

公开(公告)日：2023-08-17

申请号：US18138350

申请日：2023-04-24

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC: H10B43/27 ,  G11C16/08 ,  H01L21/02 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C16/08 ,  H01L21/0214 ,  H10B43/35

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11631697B2

公开(公告)日：2023-04-18

申请号：US17672659

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Byeung Chul Kim ,  Richard J. Hill ,  Francois H. Fabreguette ,  Gurtej S. Sandhu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. A channel material extends vertically along the stack. The channel material includes a semiconductor composition and has first segments alternating with second segments. The first segments are adjacent the wordline levels and the second segments are adjacent the insulative levels. The first segments have a first dopant distribution and the second segments have a second dopant distribution which is different from the first dopant distribution. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11605645B2

公开(公告)日：2023-03-14

申请号：US17315951

申请日：2021-05-10

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Shyam Surthi

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11524

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have primary regions of a first vertical thickness, and have terminal projections of a second vertical thickness which is greater than the first vertical thickness. The terminal projections include control gate regions. Charge-blocking regions are adjacent the control gate regions, and are vertically spaced from one another. Charge-storage regions are adjacent the charge-blocking regions and are vertically spaced from one another. Gate-dielectric material is adjacent the charge-storage regions. Channel material is adjacent the gate dielectric material. Some embodiments included methods of forming integrated assemblies.

公开(公告)号：US11563031B2

公开(公告)日：2023-01-24

申请号：US17369630

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill

IPC: H01L27/11582 ,  H01L21/768 ,  H01L45/00

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and distal regions proximate the control gate regions. The control gate regions have front surfaces, top surfaces and bottom surfaces. The top and bottoms surfaces extend back from the front surfaces. High-k dielectric material is along the control gate regions. The high-k dielectric material has first regions along the top and bottom surfaces, and has second regions along the front surfaces. The first regions are thicker than the second regions. Charge-blocking material is adjacent to the second regions of the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. Gate-dielectric material is adjacent to the charge-storage material. Channel material is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11417682B2

公开(公告)日：2022-08-16

申请号：US17230541

申请日：2021-04-14

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Shyam Surthi ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L29/792 ,  H01L29/788 ,  H01L21/02 ,  H01L27/11556

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220181334A1

公开(公告)日：2022-06-09

申请号：US17678983

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Kunal Shrotri ,  Matthew Thorum

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.