公开(公告)号：US11895236B2

公开(公告)日：2024-02-06

申请号：US18097867

申请日：2023-01-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Chin-Hung Chang

IPC: H04L9/08 ,  H04L9/32 ,  G06F12/14 ,  G11C7/24 ,  G09C1/00 ,  G11C16/22 ,  G06F12/02 ,  H03K19/003 ,  G11C7/10 ,  G11C8/20 ,  G11C16/04

CPC classification number: H04L9/0866 ,  G06F12/0246 ,  G06F12/1408 ,  G06F12/1425 ,  G09C1/00 ,  G11C7/24 ,  G11C16/22 ,  H04L9/3278 ,  G06F2212/1052 ,  G11C7/1006 ,  G11C8/20 ,  G11C16/0425 ,  G11C16/0466 ,  H03K19/003 ,  H04L2209/12

Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

公开(公告)号：US11755399B1

公开(公告)日：2023-09-12

申请号：US17752502

申请日：2022-05-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G06F11/07 ,  G06F11/10 ,  G06F3/06

CPC classification number: G06F11/076 ,  G06F3/065 ,  G06F3/0619 ,  G06F3/0656 ,  G06F11/1044 ,  G06F3/0685

Abstract: An IC is provided and includes a memory array, an address register holding at least one address of a securely stored file and configured to output three or more addresses of the securely stored filed and computation-in-memory (CIM) logic coupled with the memory array. The CIM logic is configured to perform a majority function on three or more bits of the securely stored file, wherein the three or more bits are redundantly stored in three or more different locations in the memory array and wherein the three locations are associated with the three or more addresses in the memory array.

公开(公告)号：US11749572B2

公开(公告)日：2023-09-05

申请号：US16877697

申请日：2020-05-19

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Su-Chueh Lo

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L22/32 ,  G01R31/2896 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/1623

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. An example integrated circuit device includes an integrated circuit, first type bonding pads and second type bonding pads. Each of the first type bonding pads is electrically connected to the integrated circuit and configured to be electrically connected to a corresponding external integrated circuit device. Each of the second type bonding pads is configured to have no electrical connection with the corresponding external integrated circuit device. Each of the first type bonding pads is configured to be electrically connected to a corresponding one of the second type bonding pads. A number of the first type bonding pads can be larger than a number of the second type bonding pads. Each of the second type bonding pads can have a larger pad area for probing than each of the first type bonding pads.

公开(公告)号：US11455254B2

公开(公告)日：2022-09-27

申请号：US17118239

申请日：2020-12-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Chun-Lien Su ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

IPC: G06F12/0882 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0862

Abstract: A flash memory system and a flash memory thereof are provided. The flash memory device includes a NAND flash memory and a control circuit. The NAND flash memory chip includes a cache memory, a page buffer; and an NAND flash memory array. The NAND flash memory array includes a plurality of pages, wherein each page includes a plurality of sub-pages, each sub-page has a sub-page length. The cache memory is composed of a plurality of sub cache and each sub cache corresponds to different pages of the NAND flash memory array. The page buffer is composed of a plurality of sub-page buffers and each sub-page buffer corresponds to different pages of the NAND flash memory array. The control circuit is coupled to the host and the NAND flash memory, and performs an access operation in units of one sub-page.

公开(公告)号：US11182302B2

公开(公告)日：2021-11-23

申请号：US16820795

申请日：2020-03-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Lien Su ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G06F12/08 ,  G06F12/0882 ,  G06F12/0862 ,  G11C7/22 ,  G06F9/30 ,  G06F12/0893

Abstract: A memory device, an electronic device, and associated read method are provided. The electronic device includes the memory device and a host device, which are electrically connected to each other. The memory device includes a NAND flash memory and a control logic. The NAND flash memory includes a first physical page, and the first physical page includes a plurality of first acquisition-units. The control logic is electrically connected to the NAND flash memory. The control logic receives a first-page address corresponding to the first physical page from a host device during a first page-read duration. Data stored at the plurality of first acquisition-units are respectively transferred to the host device during a second page-read duration.

公开(公告)号：US10911229B2

公开(公告)日：2021-02-02

申请号：US15864445

申请日：2018-01-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Chin-Hung Chang

IPC: G06F11/30 ,  H04L9/08 ,  H04L9/32 ,  G06F12/14 ,  G11C7/24 ,  G09C1/00 ,  G11C16/22 ,  G06F12/02 ,  H03K19/003 ,  G11C7/10 ,  G11C8/20 ,  G11C16/04

Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

公开(公告)号：US10860043B2

公开(公告)日：2020-12-08

申请号：US15658286

申请日：2017-07-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Shang-Chi Yang

IPC: G05F1/46 ,  G05F1/565

Abstract: A circuit and a method for supplying a regulated voltage to a target circuit characterized by fast changes in current loading are described. A voltage regulator supplies the regulated voltage to an output node. The voltage regulator has a transistor having a gate, a first terminal connected to a power supply terminal, and a second terminal connected to the output node of the voltage regulator. A voltage transition generator is capacitively coupled to the gate of the transistor to increase or decrease its driving power upon occurrence of an event in the target circuit indicating a change in current loading. The change in current loading can have an expected magnitude, and the voltage transition can have a magnitude that is a function of an expected magnitude of the increase or decrease in current loading.

公开(公告)号：US10725862B2

公开(公告)日：2020-07-28

申请号：US16029344

申请日：2018-07-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chia-Feng Cheng ,  Chun-Hsiung Hung

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: An integrated circuit comprising a memory array configured to store data chunks with corresponding error correction codes and error correction logic includes control logic that executes a recovery procedure to access a selected data chunk and corresponding error correction code from the memory array, to utilize the error correction logic to identify a location in the memory array of an error bit in the selected data chunk, and to access the identified location to write the corrected data. The recovery procedure is sequentially applied to a plurality of data chunks over a recovery operation region designated for a given instance of the recovery operation. Memory coupled with the control logic can store one or more recovery parameters that identify the recovery operation region in the memory.

公开(公告)号：US10032511B1

公开(公告)日：2018-07-24

申请号：US15599350

申请日：2017-05-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Chia-Jung Chen

IPC: G11C13/00

Abstract: For a memory array including a plurality of bit lines, and a set of write drivers having a number N members configured for connection in parallel to a selected set of N bit lines in the plurality of bit lines, write logic is coupled to the set of write drivers which enables a permissible number less than said number N of said members of the set of write drivers to apply a write pulse in parallel in a write operation. The write logic can dynamically assign permissible numbers to iterations in an iterative write sequence. A power source, such as charge pump circuitry, coupled to the set of write drivers can be utilized more efficiently in systems applying permissible bit write logic, enabling higher throughput or utilizing lower peak power.

公开(公告)号：US20180039784A1

公开(公告)日：2018-02-08

申请号：US15601251

申请日：2017-05-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Shih-Chang Huang

IPC: G06F21/60 ,  G06F7/58 ,  G11C13/00 ,  G11C7/24 ,  G06F12/02 ,  G06F21/31 ,  G11C16/26 ,  G06F12/14 ,  H04L9/08 ,  G06F11/10 ,  G06F21/75 ,  G11C16/10

Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.