公开(公告)号：US09455265B2

公开(公告)日：2016-09-27

申请号：US14091375

申请日：2013-11-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L27/115 ,  H01L29/66 ,  H01L27/112

CPC classification number: H01L27/11578 ,  H01L27/11206 ,  H01L27/11565 ,  H01L29/66833

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first stacked structure. The first stacked structure includes a first stacked portion disposed along a first direction, at least one second stacked portion connected with the first stacked portion and disposed along a second direction perpendicular to the first direction, and at least one third stacked portion connected with the first direction and arranged alternately with the second stacked portion along the first direction. The width of the third stacked portion is smaller than the width of the second stacked portion along the second direction.

Abstract translation: 提供半导体结构。 半导体结构包括第一堆叠结构。 第一堆叠结构包括沿着第一方向设置的第一堆叠部分，与第一堆叠部分连接并沿着垂直于第一方向的第二方向设置的至少一个第二堆叠部分，以及与第一堆叠部分连接的第一堆叠部分 方向并且沿着第一方向与第二堆叠部分交替布置。 第三堆叠部分的宽度小于沿着第二方向的第二堆叠部分的宽度。

公开(公告)号：US20160240548A1

公开(公告)日：2016-08-18

申请号：US14623630

申请日：2015-02-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device comprises plural of silicon-containing layers, string select lines (SSLs), strings, bit lines, metal strapped word lines and plural sets of multi-plugs structure. The silicon-containing layers stacked at a substrate. The SSLs are disposed on the silicon-containing layers and extend along a first direction. The strings are perpendicular to the silicon-containing layers and the SSLs and electrically connected to the SSLs. The bit lines are disposed on the SSLs extending along a second direction and electrically connected to the strings. The plural sets of multi-plugs structure are arranged along the first direction, so as to make the strings disposed between two adjacent sets of multi-plugs structure, wherein each set of multi-plugs structure has plural plugs each corresponding to and connected with one of the silicon-containing layers. Each of the metal strapped word lines is connected to the plugs that are connected to the identical silicon-containing layer.

Abstract translation: 存储器件包括多个含硅层，串选择线（SSL），串，位线，金属带状字线和多组多插头结构。 堆叠在基板上的含硅层。 SSL被设置在含硅层上并沿着第一方向延伸。 这些串垂直于含硅层和SSL并电连接到SSL。 位线布置在沿着第二方向延伸并电连接到弦的SSL上。 沿着第一方向布置多组多插头结构，以使串配置在两组相邻的多插头结构之间，其中每组多插头结构具有多个插头，每个插头对应于并与其连接 的含硅层。 每个金属带状字线连接到连接到相同的含硅层的插头。

公开(公告)号：US09401369B1

公开(公告)日：2016-07-26

申请号：US14623630

申请日：2015-02-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device comprises plural of silicon-containing layers, string select lines (SSLs), strings, bit lines, metal strapped word lines and plural sets of multi-plugs structure. The silicon-containing layers stacked at a substrate. The SSLs are disposed on the silicon-containing layers and extend along a first direction. The strings are perpendicular to the silicon-containing layers and the SSLs and electrically connected to the SSLs. The bit lines are disposed on the SSLs extending along a second direction and electrically connected to the strings. The plural sets of multi-plugs structure are arranged along the first direction, so as to make the strings disposed between two adjacent sets of multi-plugs structure, wherein each set of multi-plugs structure has plural plugs each corresponding to and connected with one of the silicon-containing layers. Each of the metal strapped word lines is connected to the plugs that are connected to the identical silicon-containing layer.

Abstract translation: 存储器件包括多个含硅层，串选择线（SSL），串，位线，金属带状字线和多组多插头结构。 堆叠在基板上的含硅层。 SSL被设置在含硅层上并沿着第一方向延伸。 这些串垂直于含硅层和SSL并电连接到SSL。 位线布置在沿着第二方向延伸并电连接到弦的SSL上。 沿着第一方向布置多组多插头结构，以使串配置在两组相邻的多插头结构之间，其中每组多插头结构具有多个插头，每个插头对应于并与其连接 的含硅层。 每个金属带状字线连接到连接到相同的含硅层的插头。

公开(公告)号：US09269660B2

公开(公告)日：2016-02-23

申请号：US13772121

申请日：2013-02-20

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Hong-Ji Lee ,  Chin-Cheng Yang

IPC: H01L23/50 ,  H01L23/522 ,  H01L23/48 ,  H01L27/112 ,  H01L21/768 ,  H01L27/02 ,  H01L27/115 ,  H01L23/00 ,  H01L27/06

CPC classification number: H01L23/50 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/19 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00

Abstract: A three-dimensional stacked IC device includes a stack of at least first, second, third and fourth contact levels at an interconnect region. Each contact level has a conductive layer and an insulation layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. A dielectric sidewall spacer circumferentially surrounds the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors only electrically contact the respective second, third and fourth conductive layers.

Abstract translation: 三维堆叠IC器件包括在互连区域处的至少第一，第二，第三和第四接触电平的堆叠。 每个接触层具有导电层和绝缘层。 第一，第二，第三和第四电导体穿过接触层叠层的部分。 第一，第二，第三和第四电导体分别与第一，第二，第三和第四导电层电接触。 电介质侧壁间隔件周向地围绕第二，第三和第四电导体，使得第二，第三和第四电导体仅电相接触相应的第二，第三和第四导电层。

公开(公告)号：US09219053B1

公开(公告)日：2015-12-22

申请号：US14324373

申请日：2014-07-07

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L23/02 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/9202 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/37001

Abstract: A three dimensional stacked multi-chip structure including M chips, a first conductive pillar, and N second conductive pillars is provided. Each chip has a common connection area and a chip-enable area, and includes a substrate and a patterned circuit layer disposed on the substrate. The patterned circuit layer includes an active element, at least one common conductive structure in the common connection area, and N chip-enable conductive structures in the chip-enable area. The first conductive pillar connects the common conductive structure of the M chips. Each second conductive pillar connects one of the N chip-enable conductive structures of the M chips. The chip-conductive areas of the M chips have different conducting states. N is large than 1, M is large than 2, and M is smaller than or equal to 2N.

Abstract translation: 提供了包括M个芯片，第一导电柱和N个第二导电柱的三维堆叠多芯片结构。 每个芯片具有公共连接区域和芯片使能区域，并且包括衬底和设置在衬底上的图案化电路层。 图案化电路层包括有源元件，公共连接区域中的至少一个公共导电结构和芯片使能区域中的N个芯片使能导电结构。 第一导电柱连接M芯片的公共导电结构。 每个第二导电柱连接M个芯片的N个芯片使能导电结构之一。 M芯片的芯片导电区域具有不同的导通状态。 N大于1，M大于2，M小于或等于2N。

公开(公告)号：US09165823B2

公开(公告)日：2015-10-20

申请号：US13736104

申请日：2013-01-08

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L29/792 ,  H01L29/788 ,  H01L29/66 ,  H01L29/40 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L21/76838 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00012

Abstract: A 3D stacking semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. N layers of stacking structures are provided. Each stacking structure includes a conductive layer and an insulating layer. A first photoresist layer is provided. The stacking structures are etched P-1 times by using the first photoresist layer as a mask. A second photoresist layer is provided. The stacking structures are etched Q-1 times by using the second photoresist layer as a mask. The first photoresist layer is trimmed along a first direction. The second photoresist layer is trimmed along a second direction. The first direction is different from the second direction. A plurality of contact points are arranged along the first and the second directions in a matrix. The included angle between the first direction and the second direction is an acute angle.

Abstract translation: 提供了3D堆叠半导体器件及其制造方法。 该制造方法包括以下步骤。 提供N层堆叠结构。 每个堆叠结构包括导电层和绝缘层。 提供第一光致抗蚀剂层。 通过使用第一光致抗蚀剂层作为掩模，将堆叠结构蚀刻P-1次。 提供第二光致抗蚀剂层。 通过使用第二光致抗蚀剂层作为掩模蚀刻层叠结构Q-1次。 第一光致抗蚀剂层沿着第一方向被修整。 第二光致抗蚀剂层沿着第二方向被修整。 第一个方向与第二个方向不同。 沿着第一和第二方向以矩阵形式布置多个接触点。 第一方向和第二方向之间的夹角是锐角。

公开(公告)号：US20150091064A1

公开(公告)日：2015-04-02

申请号：US14042776

申请日：2013-10-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L27/118

CPC classification number: H01L27/11803 ,  H01L27/10897 ,  H01L27/11529 ,  H01L27/11807 ,  H03K19/17704

Abstract: A 3D semiconductor device and a 3D logic array structure thereof are provided. The 3D semiconductor device includes an array structure, a periphery line structure and a 3D logic array structure. The array structure has Y contacts located at a side of the array structure. Y is within MN-1 to MN. Y, M and N are natural numbers. M is larger or equal to 2. The 3D logic array structure includes N sets of gate electrodes, an input electrode and Y output electrodes. Each set of the gate electrodes has M gate electrodes. The Y output electrodes connect the Y contacts. The M·N gate electrodes and the input electrode connect the periphery line structure.

Abstract translation: 提供了3D半导体器件及其3D逻辑阵列结构。 3D半导体器件包括阵列结构，外围线结构和3D逻辑阵列结构。 阵列结构具有位于阵列结构侧的Y触点。 Y在MN-1到MN之间。 Y，M和N是自然数。 M大于或等于2. 3D逻辑阵列结构包括N组栅电极，输入电极和Y输出电极。 每组栅电极具有M个栅电极。 Y输出电极连接Y触点。 M·N栅电极和输入电极连接外围线结构。

公开(公告)号：US08970040B1

公开(公告)日：2015-03-03

申请号：US14038526

申请日：2013-09-26

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76838 ,  G11C16/0483 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/11548 ,  H01L27/11575

Abstract: A method for forming a contact structure includes forming a stack of alternating active layers and insulating layers. The stack includes first and second sub stacks each with active layers separated by insulating layers. The active layers of each sub stack include an upper boundary active layer. A sub stack insulating layer is formed between the first and second sub stacks with an etching time different from the etching times of the insulating layers for a given etching process. The upper boundary active layers are accessed, after which the remainder of the active layers are accessed to create a stairstep structure of landing areas on the active layers. Interlayer conductors are formed to extend to the landing areas, the interlayer conductors separated from one another by insulating material.

Abstract translation: 形成接触结构的方法包括形成交替的有源层和绝缘层的叠层。 堆叠包括第一和第二子堆叠，每个子层具有由绝缘层分隔的活性层。 每个子堆叠的有源层包括上边界活性层。 在给定的蚀刻工艺中，在第一和第二子堆叠之间形成具有与绝缘层的蚀刻时间不同的蚀刻时间的子堆叠绝缘层。 访问上边界有源层，之后访问剩余的有源层以在有源层上创建着陆区域的初步结构。 层间导体形成为延伸到着陆区域，层间导体通过绝缘材料彼此分开。

公开(公告)号：US08934300B1

公开(公告)日：2015-01-13

申请号：US14073901

申请日：2013-11-07

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: G11C16/04 ,  G11C16/16 ,  G11C5/02 ,  G11C5/06 ,  G11C8/12 ,  G11C16/02 ,  H01L21/283 ,  G11C16/34 ,  G11C7/18

CPC classification number: G11C5/063 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/18 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/3427 ,  H01L27/0207 ,  H01L27/11529

Abstract: A memory array structure is provided. The memory array structure comprises a ring-shaped electrical pattern comprising a plurality of word lines, an array area comprising a first array, a second array and a plurality of bit lines, and a contact area comprising a plurality of contact points. The first array comprises one part of the word lines, and a first ground select line and a first string select line disposed on both sides of the word lines. The second array comprises another part of the word lines, and a second ground select line and a second string select line disposed on both sides of the word lines. The bit lines are disposed on the first array and the second array, and cross both of the first array and the second array. The word lines electrically contact with an external circuit through the contact points.

Abstract translation: 提供了存储器阵列结构。 存储器阵列结构包括包括多个字线的环形电气图案，包括第一阵列，第二阵列和多个位线的阵列区域以及包括多个接触点的接触区域。 第一阵列包括字线的一部分，以及设置在字线两侧的第一接地选择线和第一串选择线。 第二阵列包括字线的另一部分，以及设置在字线两侧的第二接地选择线和第二串选择线。 位线布置在第一阵列和第二阵列上，并且跨越第一阵列和第二阵列。 字线通过接触点与外部电路电接触。

公开(公告)号：US20140264934A1

公开(公告)日：2014-09-18

申请号：US14045573

申请日：2013-10-03

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/768 ,  H01L21/76805 ,  H01L21/76816 ,  H01L27/11551 ,  H01L27/11575 ,  H01L27/11582

Abstract: To form an interconnect conductor structure, a stack of pads, coupled to respective active layers of a circuit, is formed. Rows of interlayer conductors are formed to extend in an X direction in contact with landing areas on corresponding pads in the stack. Adjacent rows are separated from one another in a Y direction generally perpendicular to the X direction. The interlayer conductors in a row have a first pitch in the X direction. The interlayer conductors in adjacent rows are offset in the X direction by an amount less than the first pitch. Interconnect conductors are formed over and in contact with interlayer conductors. The interconnect conductors extend in the Y direction and have a second pitch less than the first pitch.

Abstract translation: 为了形成互连导体结构，形成耦合到电路的各个有源层的一叠焊盘。 层间导体的行形成为在X方向上延伸，以与堆叠中的相应焊盘上的着陆区域接触。 相邻的行在大致垂直于X方向的Y方向上彼此分离。 一行中的层间导体在X方向上具有第一间距。 相邻行中的层间导体在X方向上偏移小于第一间距的量。 互连导体形成在层间导体上并与其接触。 互连导体在Y方向上延伸并且具有小于第一间距的第二间距。