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    Semiconductor integrated circuit device
    71.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20120044775A1

    公开(公告)日：2012-02-23

    申请号：US13317846

    申请日：2011-10-31

    申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

    发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

    IPC分类号： G11C7/00

    CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

    摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

    摘要翻译： 本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND OPERATING METHOD THEREOF
    73.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND OPERATING METHOD THEREOF 有权
    半导体集成电路器件及其工作方法

    公开(公告)号：US20100177580A1

    公开(公告)日：2010-07-15

    申请号：US12687339

    申请日：2010-01-14

    申请人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki

    发明人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki

    IPC分类号： G11C7/00 ,  G11C7/02

    CPC分类号： G11C11/413 ,  G11C7/08 ,  G11C7/22 ,  G11C7/227

    摘要： Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers.

    摘要翻译： 即使使用复制位线的存储器的存储器容量更高，读出放大器使能信号的产生定时的波动也减小。 半导体集成电路器件包括多个字线，多个位线，多个普通存储器单元，访问控制电路，多个读出放大器，第一和第二复制位线，第一和第二复制 存储单元，以及第一和第二逻辑电路。 第一和第二复制存储器单元分别连接到第一和第二复制位线; 第一和第二逻辑电路的输入分别连接到第一和第二复制位线; 从第二逻辑电路的输出产生读出放大器使能信号; 并且该信号被提供给多个感测放大器。

    Semiconductor memory device and semiconductor integrated circuit device
    74.
    发明授权
    Semiconductor memory device and semiconductor integrated circuit device 有权
    半导体存储器件和半导体集成电路器件

    公开(公告)号：US07385870B2

    公开(公告)日：2008-06-10

    申请号：US11812596

    申请日：2007-06-20

    申请人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

    发明人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

    IPC分类号： G11C5/14

    CPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/22 ,  G11C8/08 ,  G11C2207/2227

    摘要： A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

    摘要翻译： 功率控制部的MOS晶体管的待机时的漏电流急剧下降，能够实现消耗功率的降低。 存储器模块具有功率控制部分。 当没有选择任何存储器垫时，功率控制部分将电源电压停止到未选择的存储器垫，字驱动器，输入输出电路，控制电路和输出电路。 在存储器模块的待机时，功率控制部分停止对功率控制部分，控制电路，预解码器电路和输入电路的电源。 以这种方式，可以显着降低在待机时功率控制部分的MOS晶体管的漏电流。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    76.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20070139072A1

    公开(公告)日：2007-06-21

    申请号：US11567774

    申请日：2006-12-07

    申请人： Masanao Yamaoka ,  Takayuki Kawahara

    发明人： Masanao Yamaoka ,  Takayuki Kawahara

    IPC分类号： H03K19/003

    CPC分类号： H03K19/0016 ,  G11C11/413

    摘要： An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.

    摘要翻译： 本发明的目的是提供一种降低驱动电路的泄漏电流的技术，该驱动电路在处于其待机状态时必须保持电位（或信息）的驱动电路。 本发明的半导体集成电路器件包括用于驱动电路块的驱动电路。 该驱动电路由具有不同栅极氧化膜厚度的栅极的双栅极晶体管构成。 当电路块处于其待机状态时，具有较薄栅极氧化膜的双栅极晶体管的栅极截止，并且具有较厚栅极氧化膜的栅极导通。 这种布置允许减少电路块和驱动电路的漏电流，同时允许驱动电路传送或切断电路块的电力。

    Semiconductor memory device and semiconductor integrated circuit device
    78.
    发明授权
    Semiconductor memory device and semiconductor integrated circuit device 有权
    半导体存储器件和半导体集成电路器件

    公开(公告)号：US07031220B2

    公开(公告)日：2006-04-18

    申请号：US10927052

    申请日：2004-08-27

    申请人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

    发明人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

    IPC分类号： G11C5/14

    CPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/22 ,  G11C8/08 ,  G11C2207/2227

    摘要： A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

    摘要翻译： 功率控制部的MOS晶体管的待机时的漏电流急剧下降，能够实现消耗功率的降低。 存储器模块具有功率控制部分。 当没有选择任何存储器垫时，功率控制部分将电源电压停止到未选择的存储器垫，字驱动器，输入输出电路，控制电路和输出电路。 在存储器模块的待机时，功率控制部分停止对功率控制部分，控制电路，预解码器电路和输入电路的电源。 以这种方式，可以显着降低在待机时功率控制部分的MOS晶体管的漏电流。