公开(公告)号：US20210343624A1

公开(公告)日：2021-11-04

申请号：US17367990

申请日：2021-07-06

Applicant: Micron Technology, Inc.

Inventor： Indra V. Chary ,  Chet E. Carter ,  Anilkumar Chandolu ,  Justin B. Dorhout ,  Jun Fang ,  Matthew J. King ,  Brett D. Lowe ,  Matthew Park ,  Justin D. Shepherdson

IPC: H01L23/48 ,  H01L21/033 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519

Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.

公开(公告)号：US10720446B2

公开(公告)日：2020-07-21

申请号：US16158039

申请日：2018-10-11

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Fei Wang ,  Chet E. Carter ,  Ian Laboriante ,  John D. Hopkins ,  Kunal Shrotri ,  Ryan Meyer ,  Vinayak Shamanna ,  Kunal R. Parekh ,  Martin C. Roberts ,  Matthew Park

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/532

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

公开(公告)号：US10651375B2

公开(公告)日：2020-05-12

申请号：US16160518

申请日：2018-10-15

Applicant: Micron Technology, Inc.

Inventor： Timothy A. Quick ,  Eugene P. Marsh ,  Stefan Uhlenbrock ,  Chet E. Carter ,  Scott E. Sills

IPC: H01L45/00

Abstract: Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. Also disclosed are fabrication methods and semiconductor devices including the disclosed memory cells.

公开(公告)号：US10573661B2

公开(公告)日：2020-02-25

申请号：US16363296

申请日：2019-03-25

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Chet E. Carter ,  Collin Howder ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L21/3213 ,  H01L29/10 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/28 ,  H01L29/49 ,  H01L27/11519 ,  H01L27/11565

Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.

公开(公告)号：US20190229127A1

公开(公告)日：2019-07-25

申请号：US16372563

申请日：2019-04-02

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Matthew Park ,  Joseph Neil Greeley ,  Chet E. Carter ,  Martin C. Roberts ,  Indra V. Chary ,  Vinayak Shamanna ,  Ryan Meyer ,  Paolo Tessariol

IPC: H01L27/11556 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region. Conductive vias extend elevationally through the vertically-alternating tiers in the second region. An elevationally-extending wall is laterally between the first and second regions. The wall comprises the programmable charge storage material and the semiconductive channel material. Other embodiments and aspects, including method, are disclosed.

公开(公告)号：US10283705B2

公开(公告)日：2019-05-07

申请号：US15915861

申请日：2018-03-08

Applicant: Micron Technology, Inc.

Inventor： Timothy A. Quick ,  Eugene P. Marsh ,  Stefan Uhlenbrock ,  Chet E. Carter ,  Scott E. Sills

IPC: H01L45/00

Abstract: Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. Also disclosed are fabrication methods and semiconductor devices including the disclosed memory cells.

公开(公告)号：US10236301B1

公开(公告)日：2019-03-19

申请号：US15890503

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Ryan M. Meyer ,  Chet E. Carter

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3205

Abstract: A method of forming an array of elevationally-extending strings of memory cells comprises forming conductively-doped semiconductor material directly above and electrically coupled to metal material. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed directly above the conductively-doped semiconductor material. Horizontally-elongated trenches are formed through the stack to the conductively-doped semiconductor material. The conductively-doped semiconductor material is oxidized through the trenches to form an oxide therefrom that is directly above the metal material. Transistor channel material is provided to extend elevationally along the alternating tiers. The wordline tiers are provided to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Charge-storage material is between the transistor channel material and the control-gate regions. Insulative charge-passage material is between the transistor channel material and the charge-storage material. A charge-blocking region is between the charge-storage material and individual of the control-gate regions.

公开(公告)号：US10229923B2

公开(公告)日：2019-03-12

申请号：US15818338

申请日：2017-11-20

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11551 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20180198063A1

公开(公告)日：2018-07-12

申请号：US15915861

申请日：2018-03-08

Applicant: Micron Technology, Inc.

Inventor： Timothy A. Quick ,  Eugene P. Marsh ,  Stefan Uhlenbrock ,  Chet E. Carter ,  Scott E. Sills

IPC: H01L45/00

CPC classification number: H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1608 ,  H01L45/1616

Abstract: Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. Also disclosed are fabrication methods and semiconductor devices including the disclosed memory cells.

公开(公告)号：US09935264B2

公开(公告)日：2018-04-03

申请号：US14677571

申请日：2015-04-02

Applicant: Micron Technology, Inc.

Inventor： Timothy A. Quick ,  Eugene P. Marsh ,  Stefan Uhlenbrock ,  Chet E. Carter ,  Scott E. Sills

IPC: H01L45/00

CPC classification number: H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1608 ,  H01L45/1616

Abstract: Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. Also disclosed are fabrication methods and semiconductor devices including the disclosed memory cells.