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    HOST CONTROLLED MEDIA TESTING OF MEMORY
    73.
    发明公开
    HOST CONTROLLED MEDIA TESTING OF MEMORY 审中-公开

    公开(公告)号：US20230290427A1

    公开(公告)日：2023-09-14

    申请号：US18120086

    申请日：2023-03-10

    Applicant: Micron Technology, Inc.

    Inventor： Danilo Caraccio ,  Daniele Balluchi ,  Niccolò Izzo ,  Alessandro Orlando

    IPC: G11C29/56 ,  G06F21/44

    CPC classification number: G11C29/56016 ,  G06F21/445

    Abstract: A controller can be configured to enable a host to control media testing on a memory device. The interface between the host and the memory can be abstract, such that the host does not have direct control over the memory. Instead, the controller can provide translation between a host protocol, such as compute express link (CXL), and a memory protocol, such as a protocol to control a dual data rate (DDR) interface. The controller can enable media test capability discovery, configuration, and/or control for the host. The controller can enable media test result reporting from the memory to the host.

    HOST CONTROLLED ELECTRONIC DEVICE TESTING
    74.
    发明公开
    HOST CONTROLLED ELECTRONIC DEVICE TESTING 审中-公开

    公开(公告)号：US20230289270A1

    公开(公告)日：2023-09-14

    申请号：US18121312

    申请日：2023-03-14

    Applicant: Micron Technology, Inc.

    Inventor： Danilo Caraccio ,  Daniele Balluchi ,  Niccolò Izzo ,  Alessandro Orlando

    IPC: G06F11/263 ,  G06F11/273 ,  G06F11/22

    CPC classification number: G06F11/263 ,  G06F11/273 ,  G06F11/2221

    Abstract: An electronic device can be configured to enable a host to indirectly control testing associated with the electronic device. The interface between the host and the electronic device can be abstract, such that the host does not have direct control over the electronic device. Examples of the electronic device include a memory device and a power management integrated circuit. The electronic device can allow the host to discover a quantity of tests supported by the electronic device and corresponding test descriptors. The electronic device can interact with the host to configure tests and/or reporting of test results.

    Timing parameter adjustment mechanisms
    75.
    发明授权
    Timing parameter adjustment mechanisms 有权

    公开(公告)号：US11721395B2

    公开(公告)日：2023-08-08

    申请号：US17518176

    申请日：2021-11-03

    Applicant: Micron Technology, Inc.

    Inventor： Marco Sforzin ,  Daniele Balluchi

    IPC: G11C11/34 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32

    CPC classification number: G11C16/10 ,  G11C16/30 ,  G11C16/32

    Abstract: Methods, systems, and devices for timing parameter adjustment mechanisms are described. The memory system may receive an access command to access a block of data. Based on receiving the access command, the memory system may determine a parameter (e.g., a timing parameter) associated with accessing the block of data. The timing parameter may indicate a duration between a first time to access a first page of the block of data and a second time to access a second page of the block of data. The memory system may perform an access operation on the block of data based on determining the timing parameter.

    DATA STRIPE PROTECTION
    76.
    发明公开
    DATA STRIPE PROTECTION 审中-公开

    公开(公告)号：US20230214119A1

    公开(公告)日：2023-07-06

    申请号：US17955907

    申请日：2022-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Marco Sforzin ,  Paolo Amato ,  Daniele Balluchi

    IPC: G06F3/06 ,  G06F11/10

    CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0673 ,  G06F11/1004

    Abstract: Systems, apparatuses, and methods related to data stripe protection are described. An error management component can process multiple read/write/recovery requests concurrently. When read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.

    Logical to physical table fragments
    77.
    发明授权
    Logical to physical table fragments 有权

    公开(公告)号：US11669461B2

    公开(公告)日：2023-06-06

    申请号：US17385380

    申请日：2021-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Daniele Balluchi ,  Dionisio Minopoli

    IPC: G06F12/1009

    CPC classification number: G06F12/1009

    Abstract: Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.

    Maintenance command interfaces for a memory system
    78.
    发明授权
    Maintenance command interfaces for a memory system 有权

    公开(公告)号：US11579970B2

    公开(公告)日：2023-02-14

    申请号：US17375832

    申请日：2021-07-14

    Applicant: Micron Technology, Inc.

    Inventor： Danilo Caraccio ,  Daniele Balluchi

    IPC: G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02

    Abstract: Methods, systems, and devices for maintenance command interfaces for a memory system are described. A host system and a memory system may be configured according to a shared protocol that supports enhanced management of maintenance operations between the host system and memory system, such as maintenance operations to resolve error conditions at a physical address of a memory system. In some examples, a memory system may initiate maintenance operations based on detections performed at the memory system, and the memory system may provide a maintenance indication for the host system. In some examples, a host system may initiate maintenance operations based on detections performed at the host system. In various examples, the described maintenance signaling may include capability signaling between the host system and memory system, status indications between the host system and memory system, and other maintenance management techniques.

    Command queuing
    79.
    发明授权
    Command queuing 有权

    公开(公告)号：US11494122B2

    公开(公告)日：2022-11-08

    申请号：US17140625

    申请日：2021-01-04

    Applicant: Micron Technology, Inc.

    Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

    IPC: G06F3/06

    Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

    CACHE ARCHITECTURE FOR A STORAGE DEVICE
    80.
    发明申请
    CACHE ARCHITECTURE FOR A STORAGE DEVICE 有权

    公开(公告)号：US20220350757A1

    公开(公告)日：2022-11-03

    申请号：US17865341

    申请日：2022-07-14

    Applicant: Micron Technology, Inc.

    Inventor： Dionisio Minopoli ,  Daniele Balluchi

    IPC: G06F13/16 ,  G06F12/10 ,  G06F12/121

    Abstract: The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being by-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions. A specific read cache architecture for a managed storage device is also disclosed to implement the above method.

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