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    CONDUCTIVE LINE CONTACT REGIONS HAVING MULTIPLE MULTI-DIRECTION CONDUCTIVE LINES AND STAIRCASE CONDUCTIVE LINE CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES
    71.
    发明申请
    CONDUCTIVE LINE CONTACT REGIONS HAVING MULTIPLE MULTI-DIRECTION CONDUCTIVE LINES AND STAIRCASE CONDUCTIVE LINE CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220108988A1

    公开(公告)日：2022-04-07

    申请号：US17060457

    申请日：2020-10-01

    Applicant: Micron Technology, Inc.

    Inventor： Byung Yoon Kim ,  Sheng Wei Yang ,  Si-Woo Lee ,  Mark Zaleski

    IPC: H01L27/108 ,  H01L27/06 ,  G11C5/10 ,  G11C5/02

    Abstract: Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.

    Epitaxtal single crystalline silicon growth for a horizontal access device
    73.
    发明授权
    Epitaxtal single crystalline silicon growth for a horizontal access device 有权

    公开(公告)号：US11289491B1

    公开(公告)日：2022-03-29

    申请号：US17035819

    申请日：2020-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Armin Saeedi Vahdat ,  Gurtej S. Sandhu ,  Scott E. Sills ,  Si-Woo Lee ,  John A. Smythe, III

    IPC: H01L27/108 ,  G11C5/06

    Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

    Methods of forming microelectronic devices
    74.
    发明授权
    Methods of forming microelectronic devices 有权

    公开(公告)号：US10985165B2

    公开(公告)日：2021-04-20

    申请号：US16543799

    申请日：2019-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Si-Woo Lee ,  Kyuseok Lee ,  Sangmin Hwang

    IPC: H01L27/108 ,  G11C5/06 ,  H01L21/768

    Abstract: A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.

    Apparatuses having memory strings compared to one another through a sense amplifier
    76.
    发明授权
    Apparatuses having memory strings compared to one another through a sense amplifier 有权

    公开(公告)号：US10347322B1

    公开(公告)日：2019-07-09

    申请号：US15900403

    申请日：2018-02-20

    Applicant: Micron Technology, Inc.

    Inventor： Tae H. Kim ,  Sangmin Hwang ,  Si-Woo Lee

    IPC: G11C11/4091 ,  G11C11/4097 ,  G11C11/22

    Abstract: Some embodiments include an apparatus having first and second comparative bitlines extending horizontally and coupled with a sense amplifier. First memory cell structures are coupled with the first comparative bitline. Each of the first memory cell structures has a first transistor associated with a first capacitor. Second memory cell structures are coupled with the second comparative bitline. Each of the second memory cell structures has a second transistor associated with a second capacitor. Each of the first capacitors has a container-shaped first node and is vertically offset from an associated first sister capacitor which is a mirror image of its associated first capacitor along a horizontal plane. Each of the second capacitors has a container-shaped first node and is vertically offset from an associated second sister capacitor which is a mirror image of its associated second capacitor along the horizontal plane.

    Methods of forming an elevationally extending conductor laterally between a pair of conductive lines
    77.
    发明授权
    Methods of forming an elevationally extending conductor laterally between a pair of conductive lines 有权

    公开(公告)号：US10134741B2

    公开(公告)日：2018-11-20

    申请号：US15652724

    申请日：2017-07-18

    Applicant: Micron Technology, Inc.

    Inventor： Guangjun Yang ,  Russell A. Benson ,  Brent Gilgen ,  Alex J. Schrinsky ,  Sanh D. Tang ,  Si-Woo Lee

    IPC: H01L21/768 ,  H01L27/108

    Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.

    Passing access line structure in a memory device
    79.
    发明授权
    Passing access line structure in a memory device 有权
    在存储设备中传递访问线路结构

    公开(公告)号：US09349737B2

    公开(公告)日：2016-05-24

    申请号：US14511371

    申请日：2014-10-10

    Applicant: Micron Technology, Inc.

    Inventor： Srinivas Pulugurtha ,  Sourabh Dhir ,  Rajesh N. Gupta ,  Sanh D. Tang ,  Si-Woo Lee ,  Haitao Liu

    IPC: H01L27/105 ,  H01L27/108 ,  G11C11/407

    CPC classification number: H01L27/10826 ,  G11C7/02 ,  G11C11/407 ,  G11C11/4097 ,  H01L27/10879

    Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.

    Abstract translation: 用于存储器件制造的方法包括在衬底上形成多个连续的翅片。 在翅片周围形成绝缘体材料。 将连续的翅片蚀刻成分段的翅片以在分段翅片之间形成暴露的区域。 在暴露区域中形成绝缘体材料，其中暴露区域中的绝缘体材料形成为高于鳍片周围的绝缘体材料。 在翅片和绝缘体材料上形成金属。 形成在暴露区域上的金属形成为比鳍片上方浅的深度。

    SINGLE CRYSTALLINE SILICON STACK FORMATION AND BONDING TO A CMOS WAFER
    80.
    发明申请
    SINGLE CRYSTALLINE SILICON STACK FORMATION AND BONDING TO A CMOS WAFER 有权

    公开(公告)号：US20250157853A1

    公开(公告)日：2025-05-15

    申请号：US19024979

    申请日：2025-01-16

    Applicant: Micron Technology, Inc.

    Inventor： Si-Woo Lee ,  Byung Yoon Kim

    IPC: H01L21/762 ,  H01L21/02 ,  H01L25/00 ,  H01L25/18

    Abstract: Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complementary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

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