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    THROUGH SILICON OPTICAL INTERCONNECTS
    71.
    发明申请
    THROUGH SILICON OPTICAL INTERCONNECTS 有权
    通过硅光学互连

    公开(公告)号：US20140131549A1

    公开(公告)日：2014-05-15

    申请号：US13771638

    申请日：2013-02-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： Kenneth Kaskoun ,  Shiqun Gu ,  Matthew M. Nowak

    IPC: H01L25/16 ,  H01L25/00

    CPC classification number: H01L25/167 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H04B10/803 ,  H01L2924/00012

    Abstract: Some implementations provide a semiconductor device that includes a first die and an optical receiver. The first die includes a back side layer having a thickness that is sufficiently thin to allow an optical signal to traverse through the back side layer. The optical receiver is configured to receive several optical signals through the back side layer of the first die. In some implementations, each optical signal originates from a corresponding optical emitter coupled to a second die. In some implementations, the back side layer is a die substrate. In some implementations, the optical signal traverses a substrate portion of the back side layer. The first die further includes an active layer. The optical receiver is part of the active layer. In some implementations, the semiconductor device includes a second die that includes an optical emitter. The second die coupled to the back side of the first die.

    Abstract translation: 一些实施方案提供包括第一管芯和光学接收器的半导体器件。 第一模具包括具有足够薄的厚度以允许光信号穿过背侧层的背面层。 光接收器被配置为通过第一管芯的背侧层接收多个光信号。 在一些实现中，每个光信号源自耦合到第二管芯的对应的光发射器。 在一些实施方式中，背面层是模具基板。 在一些实现中，光信号穿过背侧层的衬底部分。 第一裸片还包括有源层。 光接收器是有源层的一部分。 在一些实施方案中，半导体器件包括包括光发射器的第二裸片。 第二模具耦合到第一模具的背面。

    INTEGRATING THROUGH SUBSTRATE VIAS FROM WAFER BACKSIDE LAYERS OF INTEGRATED CIRCUITS
    72.
    发明申请
    INTEGRATING THROUGH SUBSTRATE VIAS FROM WAFER BACKSIDE LAYERS OF INTEGRATED CIRCUITS 有权
    通过底层VIAS从集成电路的背面层叠合

    公开(公告)号：US20140008757A1

    公开(公告)日：2014-01-09

    申请号：US13790625

    申请日：2013-03-08

    Applicant: QUALCOMM INCORPORATED

    Inventor： Vidhya Ramachandran ,  Shiqun Gu

    IPC: H01L23/498 ,  H01L21/768

    CPC classification number: H01L23/49827 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/13024

    Abstract: A semiconductor wafer has an integrated through substrate via created from a backside of the semiconductor wafer. The semiconductor wafer includes a semiconductor substrate and a shallow trench isolation (STI) layer pad on a surface of the semiconductor substrate. The semiconductor wafer also includes an inter-layer dielectric (ILD) layer formed on a contact etch stop layer, separating the ILD layer from the STI layer pad on the surface of the semiconductor substrate. The semiconductor wafer further includes a through substrate via that extends through the STI layer pad and the semiconductor substrate to couple with at least one contact within the ILD layer. The through substrate via includes a conductive filler material and a sidewall isolation liner layer. The sidewall isolation liner layer has a portion that possibly extends into, but not through, the STI layer pad.

    Abstract translation: 半导体晶片具有从半导体晶片的背面形成的集成通孔基板通孔。 半导体晶片包括在半导体衬底的表面上的半导体衬底和浅沟槽隔离（STI）层焊盘。 半导体晶片还包括形成在接触蚀刻停止层上的层间介电层（ILD）层，将ILD层与半导体衬底的表面上的STI层焊盘分离。 半导体晶片还包括穿过STI层焊盘和半导体衬底延伸穿过衬底通孔，以与ILD层内的至少一个触点耦合。 贯通基板通孔包括导电填充材料和侧壁隔离衬层。 侧壁隔离衬垫层具有可能延伸到但不穿过STI层衬垫的部分。

    VOLTAGE SWITCHABLE DIELECTRIC FOR DIE-LEVEL ELECTROSTATIC DISCHARGE (ESD) PROTECTION
    73.
    发明申请
    VOLTAGE SWITCHABLE DIELECTRIC FOR DIE-LEVEL ELECTROSTATIC DISCHARGE (ESD) PROTECTION 有权
    电压开关放电（ESD）保护的电压开关电介质

    公开(公告)号：US20130316526A1

    公开(公告)日：2013-11-28

    申请号：US13956703

    申请日：2013-08-01

    Applicant: QUALCOMM Incorporated

    Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Yiming Li

    IPC: H01L23/62

    CPC classification number: H01L23/62 ,  H01L23/29 ,  H01L23/60 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

    Abstract: A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC. A method includes depositing a voltage-switchable dielectric layer on a first die between a first terminal and a second terminal.

    Abstract translation: 可以在用于静电放电（ESD）保护的管芯上使用电压可切换电介质层。 电压切换介电层在芯片的正常操作期间用作模具的端子之间的介电层。 当在芯片的端子处发生ESD事件时，端子之间的高电压将可切换电压的电介质层切换成导电层，以允许电流放电到裸片的接地端，而不会流过电流通过电路的电路。 因此，在具有可电压切换介电层的管芯上的ESD事件期间，对管芯电路的损坏被减小或防止。 电压可切换电介质层可以沉积在管芯的背面上，用于在与第二管芯堆叠期间进行保护以形成堆叠的IC。 一种方法包括在第一端子和第二端子之间的第一管芯上沉积可电压切换介电层。

    MONOLITHIC 3-D INTEGRATION USING GRAPHENE
    75.
    发明申请
    MONOLITHIC 3-D INTEGRATION USING GRAPHENE 有权
    使用石墨的单片三维积分

    公开(公告)号：US20130082235A1

    公开(公告)日：2013-04-04

    申请号：US13644720

    申请日：2012-10-04

    Applicant: Qualcomm Incorporated

    Inventor： Shiqun Gu ,  Yang Du

    IPC: H01L27/04 ,  H01L21/50 ,  B82Y99/00

    CPC classification number: H01L27/0688 ,  H01L21/2007 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/1606

    Abstract: A monolithic three dimensional integrated circuit device includes a first layer having first active devices. The monolithic three dimensional integrated circuit device also includes a second layer having second active devices that each include a graphene portion. The second layer can be fabricated on the first layer to form a stack of active devices. A base substrate may support the stack of active devices.

    Abstract translation: 单片三维集成电路器件包括具有第一有源器件的第一层。 单片三维集成电路器件还包括具有第二有源器件的第二层，每个有源器件均包括石墨烯部分。 可以在第一层上制造第二层以形成有源器件的堆叠。 基底可以支撑有源器件的堆叠。

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