公开(公告)号：US10079097B2

公开(公告)日：2018-09-18

申请号：US14736219

申请日：2015-06-10

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Kyu-Pyung Hwang

IPC: H01G4/228 ,  H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G2/06 ,  H01G4/232

CPC classification number: H01G4/228 ,  H01G2/065 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30

Abstract: A passive discrete device may include a first asymmetric terminal and a second asymmetric terminal. The passive discrete device may further include first internal electrodes extended to electrically couple to a first side and a second side of the first asymmetric terminal. The passive discrete device may also include second internal electrodes extended to electrically couple to a first side and a second side of the second asymmetric terminal.

公开(公告)号：US09691720B2

公开(公告)日：2017-06-27

申请号：US14809983

申请日：2015-07-27

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Uei-Ming Jow ,  Jong-Hoon Lee

IPC: H01L23/58 ,  H01L49/02 ,  H01L21/765

CPC classification number: H01L23/585 ,  H01L21/765 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A multi-layer ground shield structure of interconnected elements is disclosed. The ground shield structure may include a first patterned layer of a ground shield structure, a second patterned layer of the ground shield structure, and a spacer between the first patterned layer and the second patterned layer. The first patterned layer includes first conductive elements interconnected within the first patterned layer according to a first pattern. The second patterned layer includes second conductive elements interconnected within the second patterned layer according to a second pattern.

公开(公告)号：US09653533B2

公开(公告)日：2017-05-16

申请号：US14625484

申请日：2015-02-18

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Xiaonan Zhang

IPC: H01L23/52 ,  H01L49/02 ,  H01L23/522 ,  H01G4/33 ,  H01L23/64

CPC classification number: H01L28/86 ,  H01G4/33 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/60

Abstract: An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

公开(公告)号：US20160372253A1

公开(公告)日：2016-12-22

申请号：US14746652

申请日：2015-06-22

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Jung Ho Yoon ,  Sangjo Choi ,  Xiaonan Zhang

IPC: H01F27/28 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F17/0006 ,  H01F17/0013 ,  H01F41/041 ,  H01F2027/2809

Abstract: An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.

Abstract translation: 电感器结构包括对应于电感器的第一层的第一组迹线，对应于电感器的第二层的第二组迹线，以及对应于电感器的第三层的第三组迹线，其位于 第一层和第二层。 第一组轨迹包括与第一轨迹平行的第一轨迹和第二轨迹。 第一个跟踪的维度与第二个跟踪的相应维度不同。 第二组迹线耦合到第一组迹线。 第二组迹线包括耦合到第一迹线和第二迹线的第三迹线。 第三组迹线耦合到第一组迹线。

公开(公告)号：US09502490B2

公开(公告)日：2016-11-22

申请号：US14283980

申请日：2014-05-21

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01L49/02 ,  H01L23/498 ,  H05K1/18 ,  H05K3/46 ,  H01L23/50

CPC classification number: H01L28/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/4602 ,  H01L2924/014

Abstract: A package substrate is provided that includes a core substrate and a capacitor embedded in the core substrate including a first side. The capacitor includes a first electrode and a second electrode disposed at opposite ends of the capacitor. The package also includes a first power supply metal plate extending laterally in the core substrate. The first power supply metal plate is disposed directly on the first electrode of the capacitor from the first side of the core substrate. A first via extending perpendicular to the first metal plate and connected to the first power supply metal plate from the first side of the core substrate.

Abstract translation: 提供一种封装基板，其包括芯基板和嵌入在包括第一侧的芯基板中的电容器。 电容器包括设置在电容器的相对端的第一电极和第二电极。 封装还包括在芯基板中横向延伸的第一电源金属板。 第一电源金属板从芯基板的第一侧直接设置在电容器的第一电极上。 第一通孔，其垂直于第一金属板延伸并从芯基板的第一侧连接到第一电源金属板。

公开(公告)号：US20160327590A1

公开(公告)日：2016-11-10

申请号：US14703677

申请日：2015-05-04

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang

IPC: G01R1/073 ,  G01R29/08 ,  G01R31/28

CPC classification number: G01R1/045 ,  G01R1/06722 ,  G01R1/06772 ,  G01R1/07314 ,  G01R29/08 ,  G01R31/2822

Abstract: Embodiments contained in the disclosure provide a method and apparatus for testing an electronic device. An electronic device is installed in a test socket guide. A pusher tip applies a load to the guided coaxial spring probes and forces contact with pads on the device. Test and ground signals are routed through the device and test socket. The apparatus includes a socket having at least one guided coaxial spring probe pin. A socket guide shim is positioned between the receptacle for the electronic device and the socket. A socket guide aids positioning. A pusher tip is placed on the side opposite that of the guided coaxial spring probe pins. The pusher tip mates with a pusher shim and the pusher spring. A top is then placed on the assembly and acts to compress the pusher spring and engage the guided coaxial spring probe pins with the pads on the device.

Abstract translation: 本公开内容的实施例提供了一种用于测试电子设备的方法和装置。 电子设备安装在测试插座导轨中。 推动器尖端对被引导的同轴弹簧探针施加负载，并强制与设备上的焊盘接触。 测试和接地信号通过设备和测试插座进行路由。 该装置包括具有至少一个被引导的同轴弹簧探针销的插座。 插座引导垫片位于电子设备的插座和插座之间。 插座导轨辅助定位。 推动器尖端放置在与所引导的同轴弹簧探针的相对侧的一侧。 推杆与推动垫片和推杆弹簧配合。 然后将顶部放置在组件上并且用于压缩推动器弹簧并且将引导的同轴弹簧探针针与装置上的垫接合。

公开(公告)号：US09449762B2

公开(公告)日：2016-09-20

申请号：US14272356

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H05K1/03 ,  H01G4/236 ,  H01G2/02 ,  H05K1/18 ,  H05K1/11 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H01G4/224 ,  H05K3/46 ,  H01G2/10 ,  H05K1/02

CPC classification number: H01G4/236 ,  H01G2/02 ,  H01G2/106 ,  H01G4/224 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/182 ,  H05K1/185 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/42

Abstract: Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

Abstract translation: 一些新颖的特征涉及包括具有等效串联电阻（ESR）控制的嵌入式封装衬底（EPS）电容器的衬底的封装衬底。 EPS电容器包括由电介质或绝缘薄膜材料隔开的两个导电电极和位于将电极连接到通孔的每个电极顶部的等效串联电阻（ESR）控制结构。 ESR控制结构可以包括金属层，电介质层和嵌入金属柱组中的一组金属柱，其嵌入电介质层并在电极和金属层之间延伸。 具有ESR控制结构的EPS电容器形成可嵌入封装衬底的ESR可配置EPS电容器。

公开(公告)号：US20160247761A1

公开(公告)日：2016-08-25

申请号：US14631391

申请日：2015-02-25

Applicant: QUALCOMM INCORPORATED

Inventor： Young Kyu Song ,  Hong Bok We ,  Kyu-Pyung Hwang

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/5227 ,  H01F27/2847 ,  H01F27/292 ,  H01F41/063 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L28/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated device package includes a package substrate, a die coupled to the package substrate, an encapsulation layer encapsulating the die, and at least one sheet of electrically conductive material configured to operate as an inductor. The sheet of electrically conductive material is at least partially encapsulated by the encapsulation layer. The sheet of electrically conductive material is configured to operate as a solenoid inductor. The sheet of electrically conductive material includes a first sheet portion, a second sheet portion coupled to the first sheet portion, where the first sheet portion and the second sheet portion form a first winding of the inductor, a first terminal portion coupled to the first sheet portion, and a second terminal portion coupled to the second sheet portion. The first sheet portion is formed on a first level of the sheet. The second sheet portion is formed on a second level of the sheet.

Abstract translation: 集成器件封装包括封装衬底，耦合到封装衬底的管芯，封装管芯的封装层以及配置成作为电感器工作的至少一片导电材料。 导电材料片材至少部分地被封装层封装。 导电材料片被配置为作为螺线管电感器工作。 导电材料片包括第一片部分，第二片部分，其耦合到第一片部分，第一片部分和第二片部分形成电感器的第一绕组，第一端部分耦合到第一片 部分，以及耦合到第二片部分的第二端子部分。 第一片部分形成在片材的第一层上。 第二片部分形成在片材的第二层上。

公开(公告)号：US20160240463A1

公开(公告)日：2016-08-18

申请号：US14703290

申请日：2015-05-04

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Xiaonan Zhang ,  Mario Francisco Velez

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/15311

Abstract: An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.

Abstract translation: 一种集成电路器件，包括封装衬底和耦合到封装衬底的管芯。 封装衬底包括至少一个电介质层，至少一个电介质层中的第一互连的第一叠层，以及形成在所述至少一个电介质层的至少一个侧部上的第二互连。 第一互连的第一堆叠被配置为提供用于非接地参考信号的第一电路径，其中第一互连的第一堆叠沿着封装衬底的至少一侧设置。 第二互连被配置为提供用于接地参考信号的第二电路径。

公开(公告)号：US20160141234A1

公开(公告)日：2016-05-19

申请号：US14543560

申请日：2014-11-17

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L23/498

CPC classification number: H01L23/5385 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/3436 ,  H05K3/4694 ,  H05K2203/061 ,  H01L2924/00

Abstract: An integrated device package includes a base portion, a redistribution portion, a first die and a second die. The base portion includes a photo imageable layer, a bridge that is at least partially embedded in the photo imageable layer, and a set of vias in the photo imageable layer. The bridge includes a first set of interconnects comprising a first density. The set of vias includes a second density. The redistribution portion is coupled to base portion. The redistribution portion includes at least one dielectric layer, a second set of interconnects coupled to the first set of interconnects, and a third set of interconnects coupled to the set of vias. The first die is coupled to the redistribution portion. The second die is coupled to the redistribution portion, where the first die and the second die are coupled to each other through an electrical path that includes the bridge.

Abstract translation: 集成器件封装包括基部，再分配部分，第一管芯和第二管芯。 基部包括可照像图像层，至少部分地嵌入在可照光成像层中的桥以及可照片成像层中的一组通孔。 桥包括包括第一密度的第一组互连。 该组通孔包括第二密度。 再分配部分耦合到基部。 再分配部分包括耦合到第一组互连的至少一个电介质层，第二组互连以及耦合到该组通孔的第三组互连。 第一管芯耦合到再分配部分。 第二管芯耦合到再分配部分，其中第一管芯和第二管芯通过包括桥的电路相互连接。