公开(公告)号：US20200050561A1

公开(公告)日：2020-02-13

申请号：US16546694

申请日：2019-08-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/10 ,  G11C5/02 ,  G11C11/4096 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/22 ,  G11C11/419 ,  G11C8/18

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

公开(公告)号：US20200012332A1

公开(公告)日：2020-01-09

申请号：US16418259

申请日：2019-05-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/3237 ,  G06F3/06 ,  G06F1/324 ,  G06F1/3225 ,  G06F1/12 ,  G11C7/22 ,  G06F13/16 ,  G11C11/4096 ,  G11C11/4076 ,  G11C7/10 ,  G11C7/04

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

公开(公告)号：US10509448B2

公开(公告)日：2019-12-17

申请号：US15243596

申请日：2016-08-22

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Patrick R. Gill

IPC: G06F1/20 ,  F25B49/00 ,  G06F1/26 ,  H05K7/20 ,  H01B12/02 ,  H01R4/68 ,  H01L39/02 ,  H02G15/34

Abstract: The embodiments herein describe technologies of cryogenic digital systems with a power supply located in an ambient temperature domain and logic located in a cryogenic temperature domain. A pair of conductors is operable to carry current with a voltage difference between the power supply and the logic. The pair of conductors includes a first portion thermally coupled to a temperature-regulated or temperature-controlled intermediate temperature domain. The intermediate temperature domain is less than the ambient temperature domain and greater than the cryogenic temperature domain.

公开(公告)号：US10481973B2

公开(公告)日：2019-11-19

申请号：US15907210

申请日：2018-02-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/42 ,  G11C29/44 ,  G11C5/04 ,  G11C29/04

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

公开(公告)号：US20190325936A1

公开(公告)日：2019-10-24

申请号：US16284375

申请日：2019-02-25

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

IPC: G11C11/4076 ,  G11C7/10 ,  G06F1/06 ,  G06F13/16 ,  G06F1/12 ,  G11C29/02 ,  G06F1/10 ,  G06F3/06 ,  G11C7/22 ,  G06F13/40 ,  G11C11/4096 ,  G11C11/409 ,  G11C29/50 ,  G11C5/06 ,  G11C8/18

Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

公开(公告)号：US10452478B2

公开(公告)日：2019-10-22

申请号：US15794164

申请日：2017-10-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Lawrence Lai

IPC: G11C29/00 ,  G06F11/10

Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

公开(公告)号：US20190294502A1

公开(公告)日：2019-09-26

申请号：US16290759

申请日：2019-03-01

Applicant: Rambus Inc.

Inventor： Kenneth L. Wright ,  Frederick A. Ware

IPC: G06F11/14 ,  G06F13/40 ,  G06F11/00 ,  H01L25/065 ,  H01L25/10 ,  G06F3/06 ,  H01L23/00 ,  G06F13/16

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.

公开(公告)号：US20190294348A1

公开(公告)日：2019-09-26

申请号：US16372336

申请日：2019-04-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G06F3/06 ,  G11C11/406 ,  G06F13/16 ,  G11C7/02 ,  G06Q20/00 ,  G06Q10/00

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

公开(公告)号：US10418089B2

公开(公告)日：2019-09-17

申请号：US15389407

申请日：2016-12-22

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Frederick A. Ware

IPC: G06F1/04 ,  G06F13/42 ,  G11C11/4076 ,  G11C7/10 ,  G11C7/22 ,  G11C7/04 ,  G11C29/02 ,  H04L7/00

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

公开(公告)号：US20190237130A1

公开(公告)日：2019-08-01

申请号：US16261937

申请日：2019-01-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Thomas Vogelsang

IPC: G11C11/4093 ,  G11C11/4097 ,  G11C11/4076 ,  G11C11/4094

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.