公开(公告)号：US08030668B2

公开(公告)日：2011-10-04

申请号：US11935904

申请日：2007-11-06

申请人： Digh Hisamoto ,  Shinichi Saito ,  Shinichiro Kimura

发明人： Digh Hisamoto ,  Shinichi Saito ,  Shinichiro Kimura

IPC分类号： H01L27/15

CPC分类号： H01L27/15 ,  G02B6/13 ,  G02B6/43 ,  H01L33/02 ,  H01L33/34

摘要： A light emitting diode demonstrating high luminescence efficiency and comprising a Group IV semiconductor such as silicon or germanium equivalent thereto as a basic component formed on a silicon substrate by a prior art silicon process, and a fabricating method of waveguide thereof are provided. The light emitting diode of the invention comprises a first electrode for implanting electrons, a second electrode for implanting holes, and a light emitting section electrically connected to the first and the second electrode, wherein the light emitting section is made out of single crystalline silicon and has a first surface and a second surface facing the first surface, wherein with respect to plane orientation (100) of the first and second surfaces, the light emitting section crossing at right angles to the first and second surfaces is made thinner, and wherein a material having a high refractive index is arranged around the thin film section.

摘要翻译： 提供了高发光效率的发光二极管，并且包括通过现有技术的硅工艺在硅衬底上形成的等价于其的硅或锗等IV族半导体作为基底部件，以及其波导管的制造方法。 本发明的发光二极管包括用于注入电子的第一电极，用于注入孔的第二电极和与第一和第二电极电连接的发光部分，其中发光部分由单晶硅制成， 具有面向第一表面的第一表面和第二表面，其中相对于第一表面和第二表面的平面取向（100），使与第一表面和第二表面成直角交叉的发光部分变薄，并且其中 具有高折射率的材料设置在薄膜部分周围。

公开(公告)号：US07935597B2

公开(公告)日：2011-05-03

申请号：US12912609

申请日：2010-10-26

申请人： Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

发明人： Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/0425 ,  H01L21/28282 ,  H01L21/31155 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833

摘要： Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.

摘要翻译： 提高了包括非易失性存储器的半导体器件的性能和可靠性。 非易失性存储器的存储单元包括在半导体衬底的上部上的经由第一电介质膜形成的选择栅电极和通过由具有电荷的ONO多层膜形成的第二电介质膜形成的存储栅电极 存储功能。 第一电介质膜用作栅极电介质膜，并且包括由氧化硅或氮氧化硅制成的第三电介质膜和由选择栅电极和第三电极之间形成的金属氧化物或金属硅酸盐构成的含金属元素层 电介质膜。 位于存储栅电极下方的半导体区域和第二电介质膜的电荷密度低于位于选择栅电极和第一电介质膜下方的半导体区域的电荷密度。

公开(公告)号：US20090152619A1

公开(公告)日：2009-06-18

申请号：US12368538

申请日：2009-02-10

申请人： DIGH HISAMOTO ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

发明人： DIGH HISAMOTO ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  H01L21/2815 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.

摘要翻译： 提供了一种具有分割栅极结构的非易失性半导体存储器件，其中存储栅极形成在凸形基板上，并且其侧表面用作沟道。 根据本发明的非易失性半导体存储器件即使存储单元按比例缩小，读取电流驱动功率也优异。

公开(公告)号：US20090096036A1

公开(公告)日：2009-04-16

申请号：US12248250

申请日：2008-10-09

申请人： Takashi ISHIGAKI ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

发明人： Takashi ISHIGAKI ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207

摘要： There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

摘要翻译： 提供了SOI-MISFET，其包括：SOI层; 设置在插入栅极绝缘体的SOI层上的栅电极; 以及第一升高层，其在SOI层上的栅电极的两个侧壁侧的SOI层高于栅电极，从而构成源极和漏极。 此外，还提供了一种体MISFET，包括：设置在硅衬底上的栅电极，其插入比SOI MISFET的栅极绝缘体更厚的栅极绝缘体; 以及构造在栅电极的两个侧壁处设置在半导体衬底上的源极和漏极的第二升高层。 第一升高层比升高的层厚，并且整个栅电极，SOI-MISFET的源极和漏极的一部分以及体MISFET的源极和漏极的一部分被硅化。

公开(公告)号：US20090057746A1

公开(公告)日：2009-03-05

申请号：US12187504

申请日：2008-08-07

申请人： Nobuyuki Sugll ,  Ryuta Tsuchiya ,  Shinichiro Kimura

发明人： Nobuyuki Sugll ,  Ryuta Tsuchiya ,  Shinichiro Kimura

IPC分类号： H01L29/788 ,  H01L29/06

CPC分类号： H01L27/1203 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/93

摘要： A semiconductor device having a passive element whose characteristic is adjustable even after manufacture by applying back bias voltage is provided. Formed on a main surface of a SOI substrate comprising a supporting substrate, a BOX layer, and an SOI layer is a MOS varactor comprising a gate dielectric formed on a surface of the SOI layer, a gate electrode formed on the gate dielectric, and a n+ type semiconductor region formed in the SOI layer located on both sides of the gate electrode. The MOS varactor, is configured so that capacitance formed by the SOI layer, gate dielectric, and gate electrode is varied by applying bias voltage to the supporting substrate (p type well) under the gate electrode.

摘要翻译： 提供了一种具有无源元件的半导体器件，其特征是即使在通过施加反向偏置电压制造之后也是可调节的。 在包括支撑衬底，BOX层和SOI层的SOI衬底的主表面上形成MOS变容二极管，其包括在SOI层的表面上形成的栅极电介质，形成在栅极电介质上的栅电极和 n +型半导体区域形成在位于栅电极两侧的SOI层中。 MOS变容二极管被配置为使得由SOI层，栅极电介质和栅电极形成的电容通过在栅电极下施加偏置电压到支撑衬底（p型阱）来改变。

公开(公告)号：US20090014775A1

公开(公告)日：2009-01-15

申请号：US12233670

申请日：2008-09-19

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： H01L29/00

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US20080197362A1

公开(公告)日：2008-08-21

申请号：US11935904

申请日：2007-11-06

申请人： Digh HISAMOTO ,  Shinichi Saito ,  Shinichiro Kimura

发明人： Digh HISAMOTO ,  Shinichi Saito ,  Shinichiro Kimura

IPC分类号： H01L33/00

CPC分类号： H01L27/15 ,  G02B6/13 ,  G02B6/43 ,  H01L33/02 ,  H01L33/34

摘要： A light emitting diode demonstrating high luminescence efficiency and comprising a Group IV semiconductor such as silicon or germanium equivalent thereto as a basic component formed on a silicon substrate by a prior art silicon process, and a fabricating method of waveguide thereof are provided. The light emitting diode of the invention comprises a first electrode for implanting electrons, a second electrode for implanting holes, and a light emitting section electrically connected to the first and the second electrode, wherein the light emitting section is made out of single crystalline silicon and has a first surface and a second surface facing the first surface, wherein with respect to plane orientation (100) of the first and second surfaces, the light emitting section crossing at right angles to the first and second surfaces is made thinner, and wherein a material having a high refractive index is arranged around the thin film section.

摘要翻译： 提供了高发光效率的发光二极管，并且包括通过现有技术的硅工艺在硅衬底上形成的等价于其的硅或锗等IV族半导体作为基底部件，以及其波导管的制造方法。 本发明的发光二极管包括用于注入电子的第一电极，用于注入孔的第二电极和与第一和第二电极电连接的发光部分，其中发光部分由单晶硅制成， 具有面对第一表面的第一表面和第二表面，其中相对于第一表面和第二表面的平面取向（100），使与第一表面和第二表面成直角交叉的发光部分变薄，并且其中 具有高折射率的材料设置在薄膜部分周围。

公开(公告)号：US20070274144A1

公开(公告)日：2007-11-29

申请号：US10579911

申请日：2003-11-21

申请人： Satoru Hanzawa ,  Junji Shigeta ,  Shinichiro Kimura ,  Takeshi Sakata ,  Riichiro Takemura ,  Kazuhiko Kajigaya

发明人： Satoru Hanzawa ,  Junji Shigeta ,  Shinichiro Kimura ,  Takeshi Sakata ,  Riichiro Takemura ,  Kazuhiko Kajigaya

IPC分类号： G11C7/00

CPC分类号： G11C15/04 ,  G11C15/043

摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.

摘要翻译： 在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成 比较器CP连接到预充电到高电压的匹配线HMLr。 此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。 根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。 因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。

公开(公告)号：US20070210371A1

公开(公告)日：2007-09-13

申请号：US11653832

申请日：2007-01-17

申请人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833

摘要： A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-well through an ONO layer formed below the memory gate. A sidewall-shaped silicon oxide is formed on side surfaces of the selective gate, and a sidewall-shaped silicon dioxide layer and a silicon dioxide layer are formed on side surfaces of the memory gate. The ONO layer formed below the memory gate is terminated below the silicon oxide, and prevents generation of a low breakdown voltage region in the silicon oxide near an end of the memory gate during deposition of the silicon dioxide layer.

摘要翻译： 存储单元包括布置在选择栅极的一个侧表面上的选择栅极和存储栅极。 存储器栅极包括形成在选择栅极的一个侧表面上的一个部分和与选择栅极电隔离的另一部分，以及通过形成在存储栅极下方的ONO层的p阱。 在选择栅极的侧面上形成侧壁状的氧化硅，在存储栅的侧面形成侧壁状的二氧化硅层和二氧化硅层。 形成在存储器栅下方的ONO层终止在氧化硅的下方，并且防止在沉积二氧化硅层期间在存储栅的端部附近的硅氧化物中产生低的击穿电压区域。

公开(公告)号：US20070183206A1

公开(公告)日：2007-08-09

申请号：US11727592

申请日：2007-03-27

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。