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143 条记录 (耗时 0.024 秒)

    N-channel voltage regulator
    71.
    发明授权
    N-channel voltage regulator 失效

    公开(公告)号：US5923156A

    公开(公告)日：1999-07-13

    申请号：US912875

    申请日：1997-08-15

    申请人： Stephen L. Casper

    发明人： Stephen L. Casper

    IPC分类号： G05F1/46 ,  G05F1/56 ,  G05F1/10

    CPC分类号： G05F1/465

    摘要： A voltage regulator circuit for regulating an input voltage supply. The voltage regulator includes an n-channel transistor that has a gate and a source/drain region. The source/drain region of the transistor provides an output signal for the regulator circuit. The regulator circuit also includes a pull-up device that is coupled between a pumped voltage supply and a gate of the n-channel transistor. A pull-down device is also coupled between the gate of the n-channel transistor and ground potential. The voltage regulator also includes a level sensing circuit that is responsive to the gate of the n-channel transistor. The level sensing circuit generates a control signal for a control input of the pull-down device to provide feedback control of the n-channel transistor to regulate the output of the source/drain of the n-channel transistor.

    Method and memory device for dynamic cell plate sensing with ac equilibrate
    72.
    发明授权
    Method and memory device for dynamic cell plate sensing with ac equilibrate 失效
    用于具有交流平衡的动态电池板感测的方法和存储器件

    公开(公告)号：US5862089A

    公开(公告)日：1999-01-19

    申请号：US911552

    申请日：1997-08-14

    申请人： George B. Raad ,  Stephen L. Casper

    发明人： George B. Raad ,  Stephen L. Casper

    IPC分类号： G11C7/00 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4094

    CPC分类号： G11C11/4094 ,  G11C11/4074 ,  G11C11/4091

    摘要： A memory device that uses a dynamic cell plate sensing scheme. The memory device includes an array of word lines and complementary bit line/plate line pairs. A number of memory cells are located at the intersection of selected word lines and bit line/plate line pairs. A sense amplifier is coupled to the complementary bit line/plate line pairs. The memory device also includes an equilibrate circuit that ac equilibrates a complementary bit line/plate line pair at an equilibration voltage between high and low logic levels prior to reading data. The equilibration voltage and the high and low logic levels for the memory cell are chosen such that a fluctuation in the voltage on one of the plate lines does not corrupt data stored in unaccessed memory cells coupled to the same plate line.

    摘要翻译： 一种使用动态单元板感测方案的存储器件。 存储器件包括字线阵列和互补的位线/板线对。 多个存储单元位于选定字线和位线/板线对的交点处。 读出放大器耦合到互补位线/板线对。 存储器件还包括平衡电路，其在读取数据之前在平衡电压之间平衡互补的位线/板线对在高逻辑电平和低逻辑电平之间。 选择存储器单元的平衡电压和高和低逻辑电平，使得一个板线上的电压的波动不会损坏存储在耦合到同一板线的未处理的存储器单元中的数据。

    Circuit and method for regulating a voltage
    73.
    发明授权
    Circuit and method for regulating a voltage 失效
    用于调节电压的电路和方法

    公开(公告)号：US5831419A

    公开(公告)日：1998-11-03

    申请号：US825327

    申请日：1997-03-28

    申请人： Stephen L. Casper

    发明人： Stephen L. Casper

    IPC分类号： G11C11/413 ,  G05F1/46 ,  G05F3/20 ,  G05F3/24 ,  G11C5/14 ,  G11C11/408 ,  H02M3/07 ,  G05F1/565 ,  G05B24/02 ,  G05F1/40

    CPC分类号： G05F1/465 ,  G05F3/205 ,  G11C5/147

    摘要： A circuit regulates a voltage by controlling a voltage generator. A voltage divider is coupled between the regulated voltage and a supply voltage, and generates a sense voltage. A clamp circuit is coupled to the divider, and reduces the sensitivity between the supply voltage and the regulated voltage by substantially prohibiting the voltage across itself from exceeding a predetermined value A detector circuit is coupled between the divider and the voltage generator, and provides a control signal that deactivates the generator when the sense voltage reaches a first predetermined threshold, and activates the generator when the sense voltage reaches a second predetermined threshold.

    摘要翻译： 电路通过控制电压发生器来调节电压。 分压器耦合在调节电压和电源电压之间，并产生感测电压。 钳位电路耦合到分压器，并且通过基本上禁止其自身超过预定值的电压来降低电源电压和调节电压之间的灵敏度。检测器电路耦合在分压器和电压发生器之间，并提供控制 信号，当感测电压达到第一预定阈值时停用发生器，并且当感测电压达到第二预定阈值时激活发生器。

    Two-stage fusible electrostatic discharge protection circuit
    76.
    发明授权
    Two-stage fusible electrostatic discharge protection circuit 失效
    两级可熔静电放电保护电路

    公开(公告)号：US5656967A

    公开(公告)日：1997-08-12

    申请号：US511650

    申请日：1995-08-07

    申请人： Stephen L. Casper ,  Manny Ma

    发明人： Stephen L. Casper ,  Manny Ma

    IPC分类号： H01L27/02 ,  H02H9/04 ,  H02H7/20

    CPC分类号： H01L27/0251 ,  H02H9/046

    摘要： An electrostatic discharge (ESD) protection circuit includes two stages. A first stage is operatively coupled to a metal bonding pad. This first stage is an npn transistor having a low resistance fusible element which has a fast response time. A second stage is operatively coupled in series to the first stage. The second stage provides a high-resistance path to protect the npn transistor after the fusible element has fused to into a high resistance voltage path. In addition, a semiconductor device having internal circuitry protected by this two stage ESD protection circuit is provided. The ESD protection circuit is operatively coupled between the bonding pad which is located external to the semiconductor device and the internal circuitry.

    摘要翻译： 静电放电（ESD）保护电路包括两个阶段。 第一级可操作地耦合到金属接合焊盘。 该第一级是具有低电阻可熔元件的npn晶体管，其具有快速的响应时间。 第二阶段可操作地与第一阶段耦合耦合。 第二级提供了在可熔元件融合到高电阻电压路径之后保护npn晶体管的高电阻路径。 此外，提供了具有由该两级ESD保护电路保护的内部电路的半导体器件。 ESD保护电路可操作地耦合在位于半导体器件外部的焊盘和内部电路之间。

    Single-ended sensing using global bit lines for DRAM
    77.
    发明授权
    Single-ended sensing using global bit lines for DRAM 失效
    使用DRAM的全局位线的单端感测

    公开(公告)号：US5625588A

    公开(公告)日：1997-04-29

    申请号：US471860

    申请日：1995-06-06

    申请人： Mirmajid Seyyedy ,  Stephen L. Casper

    发明人： Mirmajid Seyyedy ,  Stephen L. Casper

    IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/401 ,  G11C11/4091

    CPC分类号： G11C7/067 ,  G11C11/4091

    摘要： An integrated circuit dynamic memory device is described which stores data in memory cells as a charge on a capacitor. The memory cells can be selectively connected to a digit line. Sensing circuitry, including both p-sense and n-sense amplifiers, is connected to the digit line for sensing data stored in the memory cells. Equalization circuitry is described to equalize the sense amplifiers by connecting both nodes of the sense amplifiers to the digit line prior to sensing data stored on the memory cell.

    摘要翻译： 描述了将存储器单元中的数据作为电容器上的电荷存储的集成电路动态存储器件。 存储单元可以选择性地连接到数字线。 感测电路，包括p感测放大器和n-sense放大器，连接到数字线路，用于感测存储在存储器单元中的数据。 描述均衡电路以在感测存储在存储器单元上的数据之前将感测放大器的两个节点连接到数字线来均衡感测放大器。

    Power-up circuit responsive to supply voltage transients with signal delay
    78.
    发明授权
    Power-up circuit responsive to supply voltage transients with signal delay 失效
    响应于具有信号延迟的电源电压瞬变的上电电路

    公开(公告)号：US5557579A

    公开(公告)日：1996-09-17

    申请号：US494718

    申请日：1995-06-26

    申请人： George B. Raad ,  Stephen L. Casper

    发明人： George B. Raad ,  Stephen L. Casper

    IPC分类号： G11C5/14 ,  G11C5/00

    CPC分类号： G11C5/143

    摘要： A power-up circuit in a computer system drives a memory device such as a dynamic random access memory (DRAM) to an initial condition after the computer system is turned on or reset. The power-up circuit also advantageously drives the memory device into the initial condition upon detecting a transient such as a negative glitch in a supply voltage being provided to the memory device. The power-up circuit includes a voltage level detector which causes a power-up signal to be provided to the memory device upon detecting that the supply voltage is less than a threshold voltage of the memory device which is necessary for the memory device to operate in an operational state. The power-up circuit also includes a delay circuit which causes the power-up signal to be provided to the memory device upon detecting that the supply voltage is beginning to rise from a quiescent voltage and at least until an amount of time determined by an RC time constant of the memory device for the memory device to enter the initial condition has passed. In response to receiving the power-up signal, the memory device enters the initial condition.

    摘要翻译： 计算机系统中的上电电路在计算机系统接通或复位之后将诸如动态随机存取存储器（DRAM）的存储器件驱动到初始状态。 在检测到诸如提供给存储器件的电源电压中的负毛刺之类的瞬态时，上电电路还有利地将存储器件驱动到初始状态。 上电电路包括电压电平检测器，其在检测到电源电压小于存储器件操作所需的存储器件的阈值电压时，将上电信号提供给存储器件 操作状态。 上电电路还包括延迟电路，其在检测到电源电压从静态电压开始上升时使得上电信号被提供给存储器件，并且至少直到由RC确定的时间量 用于存储器件的存储器件的时间常数进入初始条件已经过去了。 响应于接收到上电信号，存储器件进入初始状态。

    Voltage compensating delay element
    79.
    发明授权
    Voltage compensating delay element 失效
    电压补偿延迟元件

    公开(公告)号：US5428310A

    公开(公告)日：1995-06-27

    申请号：US246881

    申请日：1994-05-19

    申请人： Stephen L. Casper ,  Daniel R. Loughmiller

    发明人： Stephen L. Casper ,  Daniel R. Loughmiller

    IPC分类号： H03K5/13 ,  H03K5/14

    CPC分类号： H03K5/133

    摘要： A signal-delaying capacitive circuit applied to a node in a microcircuit device is immunized against the variation of the supply voltage by a metal-oxide semiconductor connected in series between the node and the signal-delaying capacitive circuit. The gate of tile semiconductor is biased with a voltage signal proportional to the supply voltage, whereby the resistance of the semiconductor is increased as the supply voltage decreases; thus, isolating the capacitive circuit from the node and reducing the delay.

    摘要翻译： 施加到微电路装置中的节点的信号延迟电容电路通过串联连接在节点和信号延迟电容电路之间的金属氧化物半导体免受电源电压的变化的影响。 瓦片半导体的栅极以与电源电压成比例的电压信号偏置，由此随着电源电压的降低，半导体的电阻增加; 因此，将电容电路与节点隔离并减少延迟。