公开(公告)号：US20080238744A1

公开(公告)日：2008-10-02

申请号：US11691853

申请日：2007-03-27

申请人： Shine Chung ,  Fu-Lung Hsueh

发明人： Shine Chung ,  Fu-Lung Hsueh

IPC分类号： H03M1/66

CPC分类号： H03M1/747

摘要： A DAC cell comprising: two or more PMOS core devices coupled in series between a power supply and a steering node; a first core transistor coupled between the steering node and a complementary power supply line and controlled by a control signal; and a second core transistor coupled between the steering node and an output of the DAC cell and controlled by a logical inverse of the control signal, wherein the control signal and its logical inverse direct a current from the steering node to either the complementary power supply line or to the output of the DAC cell based on the control signal.

摘要翻译： 一种DAC单元，包括：串联耦合在电源和转向节点之间的两个或更多个PMOS核心器件; 耦合在所述转向节点和互补电源线之间并由控制信号控制的第一核心晶体管; 以及耦合在所述转向节点和所述DAC单元的输出之间并由所述控制信号的逻辑反相控制的第二核心晶体管，其中所述控制信号及其逻辑逆直接将来自所述转向节点的电流引导到所述互补电源线 或者基于控制信号到DAC单元的输出。

公开(公告)号：US20080238739A1

公开(公告)日：2008-10-02

申请号：US11691872

申请日：2007-03-27

申请人： Shine Chung ,  Fu-Lung Hsueh

发明人： Shine Chung ,  Fu-Lung Hsueh

IPC分类号： H03M1/10

CPC分类号： H03M1/1042 ,  H03M1/687

摘要： A system and method for calibrating a digital-to-analog converter (DAC) is disclosed, the method comprises providing a plurality of spare bits to each of a group of DAC bits that are designated for calibration, calibrating a first DAC bit of the group of DAC bits using its corresponding plurality of spare bits, and keeping a second DAC bit of the group of DAC bits unchanged while calibrating the first DAC bit.

摘要翻译： 公开了一种用于校准数模转换器（DAC）的系统和方法，该方法包括向被指定用于校准的一组DAC位中的每一个提供多个备用位，校准该组的第一DAC位 的DAC位使用其对应的多个备用位，并且在校准第一DAC位的同时保持DAC位组的第二DAC位不变。

公开(公告)号：US07310281B1

公开(公告)日：2007-12-18

申请号：US11514648

申请日：2006-09-01

申请人： Fu-Lung Hsueh ,  Shine Chung

发明人： Fu-Lung Hsueh ,  Shine Chung

IPC分类号： G11C7/00

CPC分类号： G11C7/1006 ,  G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4096 ,  G11C2211/4062

摘要： The present invention discloses a semiconductor memory having an array of storage cells with at least one PMOS transistor, the semiconductor memory comprising at least one mode bit for representing data stored in the array of storage cells are either true or inverted, a plurality of read-toggle drivers coupled on a plurality of data output paths for inverting the data outputs only when the mode bit indicates that the array of storage cells are storing inverted data, and a plurality of write-toggle drivers coupled on a plurality of data input paths for inverting the data inputs only when the mode bit indicates that the array of storage cells are storing inverted data and for writing back inverted data into the array of storage cells during a refreshing cycle.

摘要翻译： 本发明公开了一种具有至少一个PMOS晶体管的存储单元阵列的半导体存储器，包括用于表示存储在存储单元阵列中的数据的至少一个模式位的半导体存储器是真或反转的， 只有当模式位指示存储单元的阵列正在存储反相数据时，耦合在多个数据输出路径上的触发驱动器才能反转数据输出;以及耦合在多个数据输入路径上用于反转的多个写触发驱动器 只有当模式位指示存储单元的阵列存储反相数据并且在刷新周期期间将反相数据写入存储单元阵列时，数据输入。

公开(公告)号：US07075472B1

公开(公告)日：2006-07-11

申请号：US11180934

申请日：2005-07-13

申请人： Fu-Lung Hsueh

发明人： Fu-Lung Hsueh

IPC分类号： H03M1/12

CPC分类号： H03M1/0646 ,  H03M1/146

摘要： An analog-to-digital converter has one or more first stage comparators for generating a set of first stage comparator digital outputs, and a set of first stage comparator analog outputs upon comparing a voltage input with a set of voltage references, a switch network for selectively controlling the first stage comparator analog outputs to pass, a ratio capacitor network shared by the first stage comparators for receiving the first stage comparator analog outputs and providing a second set of intermediate analog outputs for identifying a level of the voltage input among a set of intermediate voltage levels between two voltage references, a number of second stage comparators for outputting the number of second stage comparator digital outputs, and a decoder subsystem for receiving the second stage comparator digital outputs to produce a bits of least significant bits. The ratio capacitor network is shared by more than two first stage comparators.

摘要翻译： 模数转换器具有用于产生一组第一级比较器数字输出的一个或多个第一级比较器，以及在将电压输入与一组电压参考值进行比较时的一组第一级比较器模拟输出，用于 选择性地控制第一级比较器模拟输出通过，由第一级比较器共享的用于接收第一级比较器模拟输出的比率电容网络，并提供第二组中间模拟输出，用于识别一组 两个电压基准之间的中间电压电平，用于输出第二级比较器数字输出的数量的多个第二级比较器，以及用于接收第二级比较器数字输出以产生最低有效位的位的解码器子系统。 比例电容网络由两个以上的第一级比较器共享。

公开(公告)号：US4725875A

公开(公告)日：1988-02-16

申请号：US782581

申请日：1985-10-01

申请人： Fu-Lung Hsueh

发明人： Fu-Lung Hsueh

IPC分类号： H01L27/092 ,  H01L27/11 ,  H01L27/12 ,  H01L27/02

CPC分类号： H01L27/11 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/12 ,  Y10S257/903

摘要： A memory cell has a pair of cross-coupled inverters, such as a CMOS pair. Diodes are coupled in series with the transistors to reduce the possibility of radiation-induced currents in the transistors causing a change in state of the cell by providing resistance that increases the cell time constant. The transistors and the diodes are formed in the body of a semiconducting material. The diodes require at most only a small additional cell area as compared with a cell that does not have the diodes.

摘要翻译： 存储单元具有一对交叉耦合的反相器，例如CMOS对。 二极管与晶体管串联耦合以降低晶体管中的辐射感应电流的可能性，通过提供增加电池时间常数的电阻来引起电池状态的改变。 晶体管和二极管形成在半导体材料的主体中。 与没有二极管的电池相比，二极管最多只需要一个小的附加电池区域。

公开(公告)号：US09275598B2

公开(公告)日：2016-03-01

申请号：US12859888

申请日：2010-08-20

申请人： Nang-Ping Tu ,  Fu-Lung Hsueh ,  Mingo Liu

发明人： Nang-Ping Tu ,  Fu-Lung Hsueh ,  Mingo Liu

IPC分类号： G09G3/36 ,  H03M1/68 ,  H03M1/72 ,  H03M1/76 ,  H03M1/80

CPC分类号： G09G3/3696 ,  G09G3/3688 ,  G09G2310/027 ,  H03M1/687 ,  H03M1/72 ,  H03M1/76 ,  H03M1/804 ,  H03M1/806

摘要： A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a two-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

摘要翻译： 用于响应于M位数字输入代码输出模拟电压的两级数模转换器包括具有高参考电压输入节点的两位串行电荷再分配数模转换器，用于接收高电平 参考电压和用于接收低参考电压的低参考电压输入节点，以及电压选择器。 电压选择器将高参考电压和低参考电压设置为所选电平，这取决于至少一部分M位数字输入代码。

公开(公告)号：US08981979B2

公开(公告)日：2015-03-17

申请号：US13466608

申请日：2012-05-08

申请人： Nang-Ping Tu ,  Fu-Lung Hsueh ,  Mingo Liu ,  I-Fey Wang

发明人： Nang-Ping Tu ,  Fu-Lung Hsueh ,  Mingo Liu ,  I-Fey Wang

IPC分类号： H03M1/66 ,  G09G3/36 ,  H03M1/76

CPC分类号： H03M1/66 ,  G09G3/3648 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0294 ,  H03M1/662 ,  H03M1/765

摘要： An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.

摘要翻译： 集成电路包括数模转换器（DAC）电路，其包括至少一个第一通道类型DAC和至少一个第二通道类型DAC。 集成电路包括多个采样和保持（S / H）电路。 每个S / H电路与DAC电路耦合。 S / H电路能够从DAC电路接收信号并并行输出信号。

公开(公告)号：US08835246B2

公开(公告)日：2014-09-16

申请号：US13035533

申请日：2011-02-25

申请人： Chan-Hong Chern ,  Fu-Lung Hsueh

发明人： Chan-Hong Chern ,  Fu-Lung Hsueh

IPC分类号： H01L27/088 ,  H01L27/06

CPC分类号： H01L27/0629 ,  H01L27/1207 ,  H01L28/20 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975

摘要： A method of forming an integrated circuit includes forming at least one transistor over a substrate. The at least one transistor includes a first gate dielectric structure disposed over a substrate. A work-function metallic layer is disposed over the first gate dielectric structure. A conductive layer is disposed over the work-function metallic layer. A source/drain (S/D) region is disposed adjacent to each sidewall of the first gate dielectric structure. At least one resistor structure is formed over the substrate. The at least one resistor structure includes a first doped semiconductor layer disposed over the substrate. The at least one resistor structure does not include any work-function metallic layer between the first doped semiconductor layer and the substrate.

摘要翻译： 形成集成电路的方法包括在衬底上形成至少一个晶体管。 所述至少一个晶体管包括设置在衬底上的第一栅极电介质结构。 工作功能金属层设置在第一栅极电介质结构上。 导电层设置在功函数金属层上。 源极/漏极（S / D）区域邻近第一栅极电介质结构的每个侧壁设置。 在衬底上形成至少一个电阻器结构。 所述至少一个电阻器结构包括设置在所述衬底上的第一掺杂半导体层。 至少一个电阻器结构不包括在第一掺杂半导体层和衬底之间的任何功函数金属层。

公开(公告)号：US08816732B2

公开(公告)日：2014-08-26

申请号：US13530136

申请日：2012-06-22

申请人： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

发明人： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

IPC分类号： H03L7/06

CPC分类号： H03L7/103 ,  H03L7/097 ,  H03L7/0995 ,  H03L7/1072 ,  H03L7/18 ,  H03L2207/06

摘要： A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.

摘要翻译： 电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。 校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。 校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

公开(公告)号：US20140038085A1

公开(公告)日：2014-02-06

申请号：US13562436

申请日：2012-07-31

申请人： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

发明人： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

IPC分类号： G06F17/50 ,  G03F1/68

CPC分类号： G03F7/70466 ,  G03F7/70433 ,  G06F17/5077

摘要： Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.

摘要翻译： 本公开的一些方面提供了一种自动平衡多个图案化层的掩模未对准的方法，以最小化掩模未对准的后果。 在一些实施例中，该方法定义了IC布局内的一个或多个双图案化层的布线网格。 路由网格具有沿着第一方向延伸的多个垂直网格线和沿着第二正交方向延伸的多个水平网格线。 在给定方向（例如，水平和垂直方向）上布线网格的交替线被分配不同的颜色。 然后双重图案化层上的形状沿着布线网格以不同颜色的网格线之间交替的方式布线。 通过以这种方式进行布线，减少了由掩模未对准引起的电容耦合的变化。