公开(公告)号：US11631661B2

公开(公告)日：2023-04-18

申请号：US17317216

申请日：2021-05-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tung-Heng Hsieh ,  Ting-Wei Chiang ,  Chung-Te Lin ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Sheng-Hsiung Wang

IPC: H01L27/02 ,  G06F30/39 ,  G06F30/392 ,  G06F30/398 ,  H01L23/528 ,  H01L27/092

Abstract: An integrated circuit includes a first gate electrode structure extending in a first direction and having a first portion and a second portion separated from each other. The integrated circuit further includes a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The integrated circuit further includes a conductive feature. The conductive feature includes a first section electrically connected to the second portion, wherein the first section extends in the second direction. The conductive feature further includes a second section electrically connected to the second gate electrode structure, wherein the second section extends in the second direction. The conductive feature further includes a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction.

公开(公告)号：US20230038021A1

公开(公告)日：2023-02-09

申请号：US17582001

申请日：2022-01-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Han Lin ,  Chia-En Huang ,  Han-Jong Chia ,  Yi-Ching Liu ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/522

Abstract: A memory device includes a first signal line, a second signal line, a first memory cell and a plurality of second memory cells. The first memory cell is coupled to the first signal line. Each of the second memory cells has a first terminal coupled to the first signal line through the first memory cell and a second terminal coupled to the second signal line.

公开(公告)号：US20230028561A1

公开(公告)日：2023-01-26

申请号：US17383444

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Gao-Ming Wu ,  Katherine H. CHIANG ,  Chien-Hao Huang ,  Chung-Te Lin

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate. The transistor array includes unit cells and spacers. The unit cells are disposed along rows of the transistor array extending in a first direction and columns of the transistor array extending in a second direction perpendicular to the first direction. The spacers encircle the unit cells. The unit cells include source contacts and drain contacts separated by interlayer dielectric material portions. First sections of the spacers contacting the interlayer dielectric material portions are thicker than second sections of the spacers contacting the source contacts and the drain contacts.

公开(公告)号：US20230024174A1

公开(公告)日：2023-01-26

申请号：US17383423

申请日：2021-07-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Feng Yin ,  Chia-Jung Yu ,  Pin-Cheng Hsu ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device includes a transistor. The transistor includes a gate electrode, a channel layer, a gate dielectric layer, a first source/drain region and a second source/drain region and a first spacer. The channel layer is disposed on the gate electrode. The gate dielectric layer is located between the channel layer and the gate electrode. The first source/drain region and the second source/drain region are disposed on the channel layer at opposite sides of the gate electrode, and at least one of the first and second source/drain regions includes a first portion and a second portion between the first portion and the gate electrode. The first spacer is disposed on the channel layer. The first spacer is disposed on a first sidewall of the second portion of the at least one of the first and second source/drain regions, and the first portion is disposed on the first spacer.

公开(公告)号：US20220375949A1

公开(公告)日：2022-11-24

申请号：US17880754

申请日：2022-08-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin

IPC: H01L27/112 ,  G11C17/18 ,  G11C17/16

Abstract: In some embodiments, the present disclosure relates to a one-time program memory device that includes a source-line arranged over a bottom dielectric layer. Further, a bit-line is arranged directly over the source-line in a first direction. A channel isolation structure is arranged between the source-line and the bit-line. A channel structure is also arranged between the source-line and the bit-line and is arranged beside the channel isolation structure in a second direction perpendicular to the first direction. A vertical gate electrode extends in the first direction from the bottom dielectric layer to the bit-line and is arranged beside the channel isolation structure in the second direction. The one-time program memory device further includes a gate dielectric layer arranged between the vertical gate electrode and the bit-line, the source-line, and the channel structure.

公开(公告)号：US20220375947A1

公开(公告)日：2022-11-24

申请号：US17882034

申请日：2022-08-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/1159 ,  H01L27/11597 ,  H01L29/417 ,  H01L29/66

Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tunning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.

公开(公告)号：US20220336498A1

公开(公告)日：2022-10-20

申请号：US17854701

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L27/11592 ,  H01L27/1159 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

Abstract: Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.

公开(公告)号：US11417832B2

公开(公告)日：2022-08-16

申请号：US17008000

申请日：2020-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yu-Feng Yin ,  Tai-Yen Peng ,  An-Shen Chang ,  Han-Ting Tsai ,  Qiang Fu ,  Chung-Te Lin

IPC: H01L43/02 ,  H01L21/768 ,  H01L23/522 ,  H01L43/12

Abstract: The present disclosure provides a semiconductor structure, including a substrate, including a first region and a second region adjacent to the first region, a magnetic tunnel junction (MTJ) over the first region, a spacer on a sidewall of the MTJ, a hard mask over the MTJ, a first dielectric layer laterally surrounding the spacer and the hard mask, a top electrode over the hard mask, and an etch stop stack laterally surrounding the top electrode.

公开(公告)号：US11362108B2

公开(公告)日：2022-06-14

申请号：US16904557

申请日：2020-06-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Bo-Feng Young ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L27/06 ,  H01L23/48 ,  H01L27/11 ,  H01L27/1159 ,  H01L21/822 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L27/11592

Abstract: The present disclosure provides a semiconductor structure, including: a first layer including a logic device; and a second layer over the first layer, including a first type memory device, a though silicon via (TSV) electrically connecting the logic device and the first type memory device. A method of forming semiconductor structure is also disclosed.

公开(公告)号：US20220165320A1

公开(公告)日：2022-05-26

申请号：US17103914

申请日：2020-11-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Li Chiang ,  Chung-Te Lin ,  Shy-Jay Lin ,  Tzu-Chiang Chen ,  Ming-Yuan Song ,  Hon-Sum Philip Wong

IPC: G11C11/16 ,  H01L27/22 ,  G11C11/18

Abstract: A memory device and a memory circuit is provided. The memory device includes a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ), a read word line, a selector and a write word line. The MTJ stands on the SOT layer. The read word line is electrically connected to the MTJ. The write word line is connected to the SOT layer through the selector. The write word line is electrically connected to the SOT layer when the selector is turned on, and the write word line is electrically isolated from the SOT layer when the selector is in an off state.