公开(公告)号：US12047079B2

公开(公告)日：2024-07-23

申请号：US18302178

申请日：2023-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yung-Chen Chien ,  Xiangdong Chen ,  Hui-Zhong Zhuang ,  Tzu-Ying Lin ,  Jerry Chang Jui Kao ,  Lee-Chung Lu

IPC: H03K3/3562 ,  H03K3/012 ,  H03K3/037

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/0375

Abstract: A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master stage, and a slave stage including a first feedback inverter and a first transmission gate. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the first transmission gate includes first and second input terminals configured to receive the second and third clock signals.

公开(公告)号：US12039242B2

公开(公告)日：2024-07-16

申请号：US17008067

申请日：2020-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pochun Wang ,  Jerry Chang Jui Kao ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Tzu-Ying Lin ,  Chung-Hsing Wang

IPC: G06F30/392 ,  G06F30/3953 ,  H01L27/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L27/092

CPC classification number: G06F30/392 ,  G06F30/3953 ,  H01L27/0207 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/4238 ,  H01L27/092

Abstract: A layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region and a second source/drain region extending in a first direction in a first layer, a gate electrode extending in a second direction perpendicular to the first direction in a second layer, and a first conductive line arranged in a third layer over the second layer and electrically connected to one of the first source/drain region, the second source/drain region and the gate electrode. The first cell is defined by a left cell side and a right cell side. At least one of the left cell side, the right cell side, the gate electrode and the first conductive line extends in a third direction not parallel to the first and second directions.

公开(公告)号：US12014982B2

公开(公告)日：2024-06-18

申请号：US17463203

申请日：2021-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Yu Lin ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Sheng-Hsiung Chen ,  Kuo-Nan Yang ,  Chih-Liang Chen ,  Lee-Chung Lu

IPC: G06F30/30 ,  G06F30/347 ,  G06F30/392 ,  G06F30/394 ,  H01L23/50 ,  H01L23/528 ,  H01L27/07 ,  H01L27/118 ,  H01L29/417 ,  H01L27/02

CPC classification number: H01L23/528 ,  G06F30/347 ,  G06F30/392 ,  G06F30/394 ,  H01L23/50 ,  H01L27/07 ,  H01L27/11807 ,  H01L29/41733 ,  H01L27/0207 ,  H01L2027/11879 ,  H01L2027/11881 ,  H01L2027/11887

Abstract: An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.

公开(公告)号：US11908851B2

公开(公告)日：2024-02-20

申请号：US17116915

申请日：2020-12-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shun-Li Chen ,  Chung-Te Lin ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Jung-Chan Yang

IPC: H01L29/66 ,  H01L27/02 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L21/285 ,  H01L23/532 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L27/0207 ,  H01L21/28525 ,  H01L21/28568 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5221 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53271 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/4238 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66795

Abstract: A method for forming a semiconductor device includes: forming a fin structure protruding from a substrate of the semiconductor device; forming a first conductive rail on the substrate, wherein a side of the first conductive rail facing the fin structure has a first recess and a second recess; forming a first conductive line in a same layer as the first conductive rail by filling a first conductive material into the first recess, wherein the first conductive line extends across the fin structure and wraps a portion of the fin structure; and forming a second conductive line in the same layer as the first conductive rail by filling a second conductive material into the second recess, wherein the second conductive line extends across the fin structure and contacts another portion of the fin structure.

公开(公告)号：US11870441B2

公开(公告)日：2024-01-09

申请号：US18065327

申请日：2022-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Seid Hadi Rasouli ,  Jerry Chang Jui Kao ,  Xiangdong Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Hui-Zhong Zhuang ,  Chi-Lin Liu

IPC: H03K3/037 ,  H03K19/20 ,  G06F1/12

CPC classification number: H03K3/037 ,  G06F1/12 ,  H03K19/20

Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

公开(公告)号：US11868699B2

公开(公告)日：2024-01-09

申请号：US18065299

申请日：2022-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pochun Wang ,  Yu-Jung Chang ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang

IPC: G06F30/392 ,  H01L27/092 ,  H03K19/0948 ,  H03K19/20 ,  H01L23/522 ,  H01L23/528 ,  G06F30/39

CPC classification number: G06F30/392 ,  G06F30/39 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/092 ,  H03K19/0948 ,  H03K19/20

Abstract: An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active regions extend in a first direction, are in a substrate, and are located on a first level. The first active region includes a first drain/source region and a second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact extends in a second direction, overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact extends in at least the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first drain/source region, is electrically coupled to the third drain/source region, and is located on a third level.

公开(公告)号：US11862562B2

公开(公告)日：2024-01-02

申请号：US17459756

申请日：2021-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Yu Lai ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L23/528 ,  H01L29/417 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092 ,  H01L23/552

CPC classification number: H01L23/5286 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/552 ,  H01L27/092 ,  H01L29/41725

Abstract: A circuit structure includes a substrate that includes a first transistor stack over the substrate that includes: a first transistor where the first transistor is a first conductivity type; and a second transistor, above the first transistor, where the second transistor is a second conductivity type different from the first conductivity type. The structure also includes a plurality of first conductive lines in a first metal layer above the first transistor stack, the plurality of first conductive lines electrically connected to the first transistor stack. The structure also includes a plurality of second conductive lines in a second metal layer below the substrate and underneath the first transistor stack, the plurality of second conductive lines electrically connected to the first transistor stack. The plurality of first conductive lines are configured asymmetrically with respect to the plurality of second conductive lines.

公开(公告)号：US11811407B2

公开(公告)日：2023-11-07

申请号：US17673513

申请日：2022-02-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jin-Wei Xu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

IPC: H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/02 ,  H03K3/356

CPC classification number: H03K3/356017 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/092

Abstract: A manufacturing method of an input circuit of a flip-flop including: depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first and second gate strips, a distance between the second and third gate strips, and a distance between the third and fourth gate strips equal; executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip; executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip; and directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip.

公开(公告)号：US20230268339A1

公开(公告)日：2023-08-24

申请号：US17744160

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pochun Wang ,  Chih-Yu LAI ,  Chi-Yu Lu ,  Shang-Hsuan CHIU ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

IPC: H01L27/06 ,  H01L27/02

CPC classification number: H01L27/0617 ,  H01L27/0218

Abstract: An integrated circuit including a first cell and a second cell. The first cell includes a first plurality of active areas that extend in a first direction and a first plurality of gates that extend in a second direction that crosses the first direction, the first cell having first cell edges defined by breaks in the first plurality of gates. The second cell includes a second plurality of active areas that extend in the first direction and a second plurality of gates that extend in the second direction, the second cell having second cell edges defined by breaks in the second plurality of gates. Each of the second plurality of active areas is larger than each of the first plurality of active areas and the first cell is adjacent the second cell such that the first cell edges align with the second cell edges.

公开(公告)号：US11704465B2

公开(公告)日：2023-07-18

申请号：US17106876

申请日：2020-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Hui-Zhong Zhuang ,  Chi-Yu Lu ,  Stefan Rusu

IPC: G06F30/394 ,  H01L23/528 ,  H01L21/76 ,  H03K19/094 ,  H01L23/522

CPC classification number: G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H01L23/5286 ,  H03K19/094 ,  H01L23/5226 ,  H01L2924/0002

Abstract: An integrated circuit structure includes a first and second power rail extending in a first direction and being located at a first level, a first and second set of conductive structures located at a second level and extending in a second direction, a first and second set of vias, and a first and second conductive structure located at a third level and extending in the second direction. The first set of vias coupling the first power rail to the first set of conductive structures. The second set of vias coupling the second power rail to the second set of conductive structures. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and the second set of conductive structures.