公开(公告)号：US11315785B2

公开(公告)日：2022-04-26

申请号：US16573656

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Wei-Chih Kao ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A method includes providing a semiconductor substrate; epitaxially growing a blocking layer from a top surface of the semiconductor substrate, wherein the blocking layer has a lattice constant different from the semiconductor substrate; epitaxially growing a semiconductor layer above the blocking layer; patterning the semiconductor layer to form a semiconductor fin, wherein the blocking layer is under the semiconductor fin; forming a source/drain (S/D) feature in contact with the semiconductor fin; and forming a gate structure engaging the semiconductor fin.

公开(公告)号：US11282942B2

公开(公告)日：2022-03-22

申请号：US16925703

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Kao ,  Hsin-Che Chiang ,  Yu-San Chien ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/033 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  H01L21/768

Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

公开(公告)号：US11245005B2

公开(公告)日：2022-02-08

申请号：US16868625

申请日：2020-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon-Jhy Liaw ,  Chao-Ching Cheng ,  Hung-Li Chiang ,  Shih-Syuan Huang ,  Tzu-Chiang Chen ,  I-Sheng Chen ,  Sai-Hooi Yeong

IPC: H01L29/76 ,  H01L31/113 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423

Abstract: Methods for forming semiconductor structures are provided. The method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate and patterning the first semiconductor layers and the second semiconductor layers to form a first fin structure. The method further includes forming a first trench in the first fin structure and forming a first source/drain structure in the first trench. The method further includes partially removing the first source/drain structure to form a second trench in the first source/drain structure and forming a first contact in the second trench.

公开(公告)号：US20210391327A1

公开(公告)日：2021-12-16

申请号：US16899592

申请日：2020-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-San Chien ,  Chun-Sheng Liang ,  Jhon-Jhy Liaw ,  Kuo-Hua Pan ,  Hsin-Che Chiang

IPC: H01L27/092 ,  H01L21/8238

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of hybrid fins, a gate, and a dielectric structure. The substrate includes a plurality of fins. The plurality of hybrid fins are respectively disposed between the plurality of fins. The gate covers portions of the plurality of fins and the plurality of hybrid fins. The dielectric structure lands on one of the plurality of hybrid fins to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the one of the plurality of hybrid fins.

公开(公告)号：US20210280711A1

公开(公告)日：2021-09-09

申请号：US17328016

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-San Chien ,  Hsin-Che Chiang ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/02

Abstract: An embodiment method includes forming a semiconductor liner layer on a first fin structure and on a second fin structure and forming a first capping layer on the semiconductor liner layer disposed on the first fin structure. The method further includes forming a second capping layer on the semiconductor liner layer disposed on the first fin structure, where a composition of the first capping layer is different from a composition of the second capping layer. The method additionally includes performing a thermal process on the first capping layer, the second capping layer, and the semiconductor liner layer to form a first channel region in the first fin structure and a second channel region in the second fin structure. A concentration profile of a material of the first channel region is different from a concentration profile of a material of the second channel region.

公开(公告)号：US11037831B2

公开(公告)日：2021-06-15

申请号：US16737447

申请日：2020-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Buo-Chin Hsu ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

公开(公告)号：US10998237B2

公开(公告)日：2021-05-04

申请号：US16853474

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Buo-Chin Hsu ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

公开(公告)号：US10854506B2

公开(公告)日：2020-12-01

申请号：US16224155

申请日：2018-12-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Sheng Liang ,  Wei-Chih Kao ,  Hsin-Che Chiang ,  Kuo-Hua Pan

IPC: H01L23/522 ,  H01L23/528 ,  H01L29/49 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate, a gate stack over the substrate, an insulating structure over the gate stack, a conductive via in the insulating structure, and an contact etch stop layer (CESL) over the insulating structure. The insulating structure has an air slit therein. The conductive via is electrically connected to the gate stack. A portion of the CESL is exposed in the air slit.

公开(公告)号：US10741558B2

公开(公告)日：2020-08-11

申请号：US16357682

申请日：2019-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/24 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/06

Abstract: A method of forming a semiconductor device includes providing a fin extruding from a substrate, the fin having first epitaxial layers alternating with second epitaxial layers, the first epitaxial layers including a first semiconductor material, the second epitaxial layers including a second semiconductor material different from the first semiconductor material; etching sidewalls of at least one of the second epitaxial layers in a channel region of the fin, such that a width of the at least one of the second epitaxial layers in the channel region after etching is smaller than a width of the first epitaxial layers contacting the at least one of the second epitaxial layers; and forming a gate stack over of the fin, the gate stack engaging both the first epitaxial layers and the second epitaxial layers.

公开(公告)号：US10510751B2

公开(公告)日：2019-12-17

申请号：US15686860

申请日：2017-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Che Tsai ,  Min-Yann Hsieh ,  Hua Feng Chen ,  Kuo-Hua Pan

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/45 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/764 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L21/306 ,  H01L21/308 ,  H01L29/08

Abstract: Embodiments of the disclosure provide a semiconductor device including a substrate, an insulating layer formed over the substrate, a plurality of fins formed vertically from a surface of the substrate, the fins extending through the insulating layer and above a top surface of the insulating layer, a gate structure formed over a portion of fins and over the top surface of the insulating layer, a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting the fin, a dielectric layer formed over the insulating layer, a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material, and a second contact trench extending a second depth into the dielectric layer, the second contact trench containing the electrical conductive material, and the second depth is greater than the first depth.