公开(公告)号：US11532498B2

公开(公告)日：2022-12-20

申请号：US16934394

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Hui-Min Huang ,  Ai-Tee Ang ,  Yu-Peng Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/683 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L25/10 ,  H01L21/56 ,  H01L25/065

Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.

公开(公告)号：US20220336276A1

公开(公告)日：2022-10-20

申请号：US17809960

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Song-Bor Lee ,  Wen-Hsiung Lu ,  Po-Hao Tsai ,  Wen-Che Chang

IPC: H01L21/768 ,  H01L23/00

Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

公开(公告)号：US11456266B2

公开(公告)日：2022-09-27

申请号：US17019173

申请日：2020-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ching-Yu Chang ,  Ming-Da Cheng ,  Ming-Hui Weng

IPC: H01L23/00 ,  C08G73/10

Abstract: A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.

公开(公告)号：US20220223550A1

公开(公告)日：2022-07-14

申请号：US17323506

申请日：2021-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Ting-Li Yang ,  Po-Hao Tsai ,  Chien-Chen Li ,  Ming-Da Cheng

IPC: H01L23/00 ,  H01L23/31

Abstract: In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.

公开(公告)号：US20210375675A1

公开(公告)日：2021-12-02

申请号：US17085731

申请日：2020-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Song-Bor Lee ,  Wen-Hsiung Lu ,  Po-Hao Tsai ,  Wen-Che Chang

IPC: H01L21/768 ,  H01L23/00

Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

公开(公告)号：US11133285B2

公开(公告)日：2021-09-28

申请号：US16360411

申请日：2019-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Yu-Chih Liu ,  Hui-Min Huang ,  Wei-Hung Lin ,  Jing Ruei Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/29

Abstract: The present disclosure, in some embodiments, relates to a method of forming a package. The method includes coupling a first package component to a second package component using a first set of conductive elements. A first polymer-comprising material is formed over the second package component and surrounding the first set of conductive elements. The first polymer-comprising material is cured to solidify the first polymer-comprising material. A part of the first polymer-comprising material is removed to expose an upper surface of the second package component. The second package component is coupled to a third package component using a second set of conductive elements that are formed onto the upper surface of the second package component.

公开(公告)号：US11101233B1

公开(公告)日：2021-08-24

申请号：US16868909

申请日：2020-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-En Yen ,  Chin-Wei Kang ,  Kai-Jun Zhan ,  Wen-Hsiung Lu ,  Cheng-Jen Lin ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L21/48 ,  H01L23/552 ,  H01L23/00

Abstract: A method for forming a semiconductor device is provided. The method includes providing a substrate. The method includes forming a mask layer over a surface of the substrate. The mask layer has an opening over a portion of the surface. The method includes depositing a conductive layer over the surface and the mask layer. The method includes removing the mask layer and the conductive layer over the mask layer. The conductive layer remaining after the removal of the mask layer and the conductive layer over the mask layer forms a conductive pad. The method includes bonding a device to the conductive pad through a solder layer. The conductive pad is embedded in the solder layer.

公开(公告)号：US20210233854A1

公开(公告)日：2021-07-29

申请号：US17215079

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Da Cheng

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

公开(公告)号：US20210202335A1

公开(公告)日：2021-07-01

申请号：US17201445

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Fan Huang ,  Chih-Wei Lin ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC: H01L23/31 ,  H01L25/10 ,  H01L21/56 ,  H01L23/528 ,  H01L21/768 ,  H01L21/82 ,  H01L23/04 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die.

公开(公告)号：US10658323B2

公开(公告)日：2020-05-19

申请号：US16398119

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Hao-Jan Pei ,  Chih-Chiang Tsao ,  Wei-Yu Chen ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/11 ,  H01L25/10 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683

Abstract: A package structure is provided. The package structure includes a semiconductor die and a protective layer surrounding the semiconductor die. The package structure also includes a conductive structure and a warpage-control element over a same side of the protective layer. A bottom surface of the warpage-control element is higher than a bottom surface of the conductive structure. The bottom surface of the warpage-control element is lower than a top surface of the conductive bump.