公开(公告)号：US20240429101A1

公开(公告)日：2024-12-26

申请号：US18489994

申请日：2023-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Chun Liao ,  Chih-Wei Lin ,  Ching-Hua Hsieh ,  Wen-Chih Chiou

IPC: H01L21/78 ,  H01L21/66

Abstract: A method includes forming a database, finding a plurality of dicing marks on a wafer, wherein patterns of the plurality of dicing marks match a pattern in the database, measuring a die pitch of the wafer according to a patch of adjacent two of the plurality of dicing marks, and determining kerf centers of the wafer based on the plurality of dicing marks. The measuring the die pitch and the determining the kerf centers are performed on a same wafer-holding platform. The wafer is diced into a plurality of dies, and the dicing is performed aligning to the kerf centers.

公开(公告)号：US20240387346A1

公开(公告)日：2024-11-21

申请号：US18366255

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Tsao ,  Chao-Wei Chiu ,  Hsin Liang Chen ,  Chia-Shen Cheng ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

Abstract: Embodiments include a device. The device includes an interposer, a package substrate, and conductive connectors bonding the package substrate to the interposer. Each of the conductive connectors have convex sidewalls. A first subset of the conductive connectors are disposed in a center of the package substrate in a top-down view. A second subset of the conductive connectors are disposed in an edge/corner of the package substrate in the top-down view. Each of the second subset of the conductive connectors have a greater height than each of the first subset of the conductive connectors.

公开(公告)号：US11482491B2

公开(公告)日：2022-10-25

申请号：US15877398

申请日：2018-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chih-Hua Chen ,  Ching-Hua Hsieh ,  Hsiu-Jen Lin ,  Yu-Chih Huang ,  Yu-Peng Tsai ,  Chia-Shen Cheng ,  Chih-Chiang Tsao ,  Jen-Jui Yu

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/522 ,  H01L23/538 ,  H01L21/683

Abstract: A package structure includes an insulating encapsulation, at least one die, and conductive structures. The at least one die is encapsulated in the insulating encapsulation. The conductive structures are located aside of the at least one die and surrounded by the insulating encapsulation, and at least one of the conductive structures is electrically connected to the at least one die. Each of the conductive structures has a first surface, a second surface opposite to the first surface and a slant sidewall connecting the first surface and the second surface, and each of the conductive structures has a top diameter greater than a bottom diameter thereof, and wherein each of the conductive structures has a plurality of pores distributed therein.

公开(公告)号：US11309226B2

公开(公告)日：2022-04-19

申请号：US16719955

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Min Lin ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Sheng-Hsiang Chiu ,  Sheng-Feng Weng ,  Yao-Tong Lai

IPC: H01L23/31 ,  H01L25/16 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

Abstract: Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.

公开(公告)号：US11049832B2

公开(公告)日：2021-06-29

申请号：US16876371

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan Pei ,  Chih-Chiang Tsao ,  Wei-Yu Chen ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/00 ,  H01L25/10 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683 ,  H01L25/11

Abstract: A method for forming a package structure is provided. The method includes forming a protective layer to surround a semiconductor die and forming a conductive structure over the protective layer. The method also includes disposing a polymer-containing material over the protective layer to partially surround the conductive structure. The method further includes curing the polymer-containing material to form a warpage-control element.

公开(公告)号：US11031376B2

公开(公告)日：2021-06-08

申请号：US16513739

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsaing-Pin Kuan ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Ching-Yao Lin ,  Chun-Yen Lan ,  Kai-Ming Chiang

IPC: H01L23/48 ,  H01L29/40 ,  H01L25/065 ,  H01L23/00 ,  H01L23/28 ,  H01L25/00 ,  H01L23/538 ,  H01L23/488

Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.

公开(公告)号：US20200321279A1

公开(公告)日：2020-10-08

申请号：US16904026

申请日：2020-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Lin Su ,  Ching-Hua Hsieh ,  Huang-Ming Chen ,  Hsueh Wen Tsau

IPC: H01L23/535 ,  H01L29/49 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485 ,  H01L29/66 ,  H01L21/768 ,  H01L21/28

Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.

公开(公告)号：US20200258801A1

公开(公告)日：2020-08-13

申请号：US16858737

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Cheng Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/367 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

公开(公告)号：US20190333870A1

公开(公告)日：2019-10-31

申请号：US15964091

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Hao-Cheng Hou ,  Jung-Wei Cheng

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/02 ,  H01L21/48

Abstract: A package structure including a semiconductor die, a warpage control layer, an insulating encapsulant and a redistribution layer is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The warpage control layer is disposed on the backside surface of the semiconductor die, wherein the warpage control layer comprises a material having a Young's Modulus of 100 GPa or more. The insulating encapsulant is encapsulating the semiconductor die and the warpage control layer. The redistribution layer is located on the insulating encapsulant and over the active surface of the semiconductor die.

公开(公告)号：US10157846B2

公开(公告)日：2018-12-18

申请号：US15292762

申请日：2016-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao Chen ,  Chih-Wei Lin ,  Tsung-Hsien Chiang ,  Ming-Da Cheng ,  Ching-Hua Hsieh

IPC: H01L21/44 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

Abstract: Structures and formation methods of a chip package are provided. The method includes disposing a semiconductor die over a carrier substrate and forming a protection layer over the carrier substrate to surround the semiconductor die. The method also includes forming a dielectric layer over the protection layer and the semiconductor die. The method further includes cutting an upper portion of the dielectric layer to improve flatness of the dielectric layer. In addition, the method includes forming a conductive layer over the dielectric layer after cutting the upper portion of the dielectric layer.