公开(公告)号：US10811377B2

公开(公告)日：2020-10-20

申请号：US16194927

申请日：2018-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hung Chen ,  Yu-Nu Hsu ,  Chun-Chen Liu ,  Heng-Chi Huang ,  Chien-Chen Li ,  Shih-Yen Chen ,  Cheng-Nan Hsieh ,  Kuo-Chio Liu ,  Chen-Shien Chen ,  Chin-Yu Ku ,  Te-Hsun Pang ,  Yuan-Feng Wu ,  Sen-Chi Chiang

IPC: H01L23/20 ,  H01L23/498 ,  H01L23/00

Abstract: A package structure is provided. The package structure includes a first bump structure formed over a substrate, a solder joint formed over the first bump structure and a second bump structure formed over the solder joint. The first bump structure includes a first pillar layer formed over the substrate and a first barrier layer formed over the first pillar layer. The first barrier layer has a first protruding portion which extends away from a sidewall surface of the first pillar layer, and a distance between the sidewall surface of the first pillar layer and a sidewall surface of the first barrier layer is in a range from about 0.5 μm to about 3 μm. The second bump structure includes a second barrier layer formed over the solder joint and a second pillar layer formed over the second barrier layer, wherein the second barrier layer has a second protruding portion which extends away from a sidewall surface of the second pillar layer.

公开(公告)号：US11862588B2

公开(公告)日：2024-01-02

申请号：US17323506

申请日：2021-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Ting-Li Yang ,  Po-Hao Tsai ,  Chien-Chen Li ,  Ming-Da Cheng

IPC: H01L23/31 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/16 ,  H01L2224/0236 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/16225

Abstract: In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.

公开(公告)号：US10170429B2

公开(公告)日：2019-01-01

申请号：US15431802

申请日：2017-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Heng-Chi Huang ,  Chien-Chen Li ,  Kuo-Lung Li ,  Cheng-Liang Cho ,  Che-Jung Chu ,  Kuo-Chio Liu

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/68 ,  H01L21/683

Abstract: Package structures and methods for forming the same are provided. A package structure includes a package component including a first bump. The package structure also includes an intermetallic compound (IMC) on the first bump. The package structure further includes an integrated circuit die including a second bump on the IMC. The integrated circuit die and the package component are bonded together through the first bump and the second bump. The IMC extends from the first bump to the second bump to provide good physical and electrical connections between the first bump and the second bump.

公开(公告)号：US20240096827A1

公开(公告)日：2024-03-21

申请号：US18526057

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Ting-Li Yang ,  Po-Hao Tsai ,  Chien-Chen Li ,  Ming-Da Cheng

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/16 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/16225

Abstract: In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.

公开(公告)号：US20230411307A1

公开(公告)日：2023-12-21

申请号：US17841275

申请日：2022-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Yi Lin ,  Kuang-Chun Lee ,  Chien-Chen Li ,  Chien-Li Kuo ,  Kuo-Chio Liu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L23/3185 ,  H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563

Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes a large package component, such as a CoWoS, adhered to a large package substrate, such as a printed circuit board, an underfill material disposed between the large package component and the large package substrate, and a stress-release structure with high elongation values formed from photolithography encapsulated by the underfill material. The stress-release structure helping to reduce stress in the underfill material to reduce the risk of underfill cracking caused by the difference in coefficients of thermal expansion between the large package component and the large package substrate.

公开(公告)号：US20230377905A1

公开(公告)日：2023-11-23

申请号：US17751234

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Li Kuo ,  Chien-Chen Li ,  Kuo-Chio Liu ,  Kuang-Chun Lee ,  Wen-Yi Lin

IPC: H01L21/48 ,  H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L21/486 ,  H01L23/481 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/73 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/15311 ,  H01L2224/73267

Abstract: In an embodiment, a device includes: an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure on the encapsulant, the redistribution structure including a redistribution line, the redistribution line physically and electrically coupled to the die connector of the integrated circuit die, the redistribution line electrically isolated from the first through via, the redistribution line crossing over the first through via.

公开(公告)号：US20220223550A1

公开(公告)日：2022-07-14

申请号：US17323506

申请日：2021-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Ting-Li Yang ,  Po-Hao Tsai ,  Chien-Chen Li ,  Ming-Da Cheng

IPC: H01L23/00 ,  H01L23/31

Abstract: In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.

公开(公告)号：US11088108B2

公开(公告)日：2021-08-10

申请号：US16454350

申请日：2019-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Yao Yang ,  Ling-Wei Li ,  Yu-Jui Wu ,  Cheng-Lin Huang ,  Chien-Chen Li ,  Lieh-Chuan Chen ,  Che-Jung Chu ,  Kuo-Chio Liu

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/768

Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.

公开(公告)号：US20250118690A1

公开(公告)日：2025-04-10

申请号：US18482122

申请日：2023-10-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Yi Lin ,  Kan-Ju Yang ,  Kai-Cheng Chen ,  Chien-Li Kuo ,  Chien-Chen Li

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31

Abstract: A semiconductor package includes: a die having a conductive pad at a first side of the die; and a redistribution structure over the first side of the die and electrically coupled to the die. The redistribution structure includes: a first dielectric layer including a first dielectric material; a first via in the first dielectric layer, where the first via is electrically coupled to the conductive pad of the die; and a first dielectric structure embedded in the first dielectric layer, where the first dielectric structure includes a second dielectric material different from the first dielectric material, where the first dielectric structure laterally surrounds the first via and contacts sidewalls of the first via.

公开(公告)号：US20240071950A1

公开(公告)日：2024-02-29

申请号：US17898075

申请日：2022-08-29

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Wen-Yi Lin ,  Kuang-Chun Lee ,  Chien-Chen Li ,  Chien-Li Kuo ,  Kuo-Chio Liu

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/4817 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16221 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001

Abstract: Integrated circuit packages and methods of forming the same are discussed. In an embodiment, a device includes: a package substrate; a semiconductor device attached to the package substrate; an underfill between the semiconductor device and the package substrate; and a package stiffener attached to the package substrate, the package stiffener includes: a main body extending around the semiconductor device and the underfill in a top-down view, the main body having a first coefficient of thermal expansion; and pillars in the main body, each of the pillars extending from a top surface of the main body to a bottom surface of the main body, each of the pillars physically contacting the main body, the pillars having a second coefficient of thermal expansion, the second coefficient of thermal expansion being less than the first coefficient of thermal expansion.