Plasmon-enhanced electromagnetic-radiation-emitting devices and methods for fabricating the same
    71.
    发明申请
    Plasmon-enhanced electromagnetic-radiation-emitting devices and methods for fabricating the same 有权
    等离子体增强型电磁辐射发射装置及其制造方法

    公开(公告)号:US20090028493A1

    公开(公告)日:2009-01-29

    申请号:US11881266

    申请日:2007-07-26

    IPC分类号: G02B6/12 H01L33/00 H01L21/00

    摘要: Various embodiments of the present invention are directed to surface-plasmon-enhanced electromagnetic-radiation-emitting devices and to methods of fabricating these devices. In one embodiment of the present invention, an electromagnetic-radiation-emitting device comprises a multilayer core, a metallic device layer, and a substrate. The multilayer core has an inner layer and an outer layer, wherein the outer layer is configured to surround at least a portion of the inner layer. The metallic device layer is configured to surround at least a portion of the outer layer. The substrate has a bottom conducting layer in electrical communication with the inner layer and a top conducting layer in electrical communication with the metallic device layer such that the exposed portion emits surface-plasmon-enhanced electromagnetic radiation when an appropriate voltage is applied between the bottom conducting layer and the top conducting layer.

    摘要翻译: 本发明的各种实施例涉及表面等离子体增强的电磁辐射发射装置以及制造这些装置的方法。 在本发明的一个实施例中,电磁辐射发射装置包括多层芯,金属器件层和衬底。 多层芯具有内层和外层,其中外层被构造成围绕内层的至少一部分。 金属器件层被配置为围绕外层的至少一部分。 衬底具有与内层电连通的底部导电层和与金属器件层电连通的顶部导电层,使得当在底部导电之间施加适当的电压时,暴露部分发射表面等离子体增强的电磁辐射 层和顶部导电层。

    Methods for coupling diamond structures to photonic devices
    73.
    发明申请
    Methods for coupling diamond structures to photonic devices 有权
    将金刚石结构耦合到光子器件的方法

    公开(公告)号:US20080303049A1

    公开(公告)日:2008-12-11

    申请号:US12228039

    申请日:2008-08-08

    IPC分类号: H01L33/00 H01L21/00

    CPC分类号: G02B6/122 G02F2202/32

    摘要: Various embodiments of the present invention are directed to methods for coupling semiconductor-based photonic devices to diamond. In one embodiment of the present invention, a photonic device is optically coupled with a diamond structure. The photonic device comprises a semiconductor material and is optically coupled with the diamond structure with an adhesive substance that adheres the photonic device to the diamond structure. A method for coupling the photonic device with the diamond structure is also provided. The method comprises: depositing a semiconductor material on the diamond structure; forming the photonic device in the semiconductor material so that the photonic device couples with the diamond structure; and adhering the photonic device to the diamond structure.

    摘要翻译: 本发明的各种实施例涉及将基于半导体的光子器件耦合到金刚石的方法。 在本发明的一个实施例中,光子器件与金刚石结构光学耦合。 光子器件包括半导体材料,并与金刚石结构光学耦合,粘合剂物质将光子器件粘附到金刚石结构上。 还提供了一种用于将光子器件与金刚石结构耦合的方法。 该方法包括:在金刚石结构上沉积半导体材料; 在半导体材料中形成光子器件,使得光子器件与金刚石结构耦合; 并将光子器件粘附到金刚石结构上。

    Capacitively coupling layers of a multilayer device
    74.
    发明申请
    Capacitively coupling layers of a multilayer device 有权
    电容耦合多层器件的层

    公开(公告)号:US20080170820A1

    公开(公告)日:2008-07-17

    申请号:US11652220

    申请日:2007-01-11

    IPC分类号: G02B6/12

    摘要: A multilayer device includes an electronic device layer, a first electrode associated with the electronic device layer, an optical layer, a second electrode associated with the optical layer, and an insulator layer provided between the first and second electrodes. The first and second electrodes are capacitively coupled to each other to facilitate electrical communication between the electronic device layer and the optical layer through transmission of an electrical signal between the first and second electrodes. The electrical signal may be transmitted through the insulator layer. In addition, the electronic device layer and the optical layer may be in electrical communication with each other through capacitive coupling of the first electrode and the second electrode.

    摘要翻译: 多层器件包括电子器件层,与电子器件层相关联的第一电极,光学层,与光学层相关联的第二电极以及设置在第一和第二电极之间的绝缘体层。 第一和第二电极彼此电容耦合,以通过在第一和第二电极之间传输电信号来促进电子器件层与光学层之间的电连通。 电信号可以透过绝缘体层。 此外,电子器件层和光学层可以通过第一电极和第二电极的电容耦合而彼此电连通。

    Binary arrays of nanoparticles for nano-enhanced Raman scattering molecular sensors
    76.
    发明授权
    Binary arrays of nanoparticles for nano-enhanced Raman scattering molecular sensors 有权
    用于纳米增强拉曼散射分子传感器的二元纳米颗粒阵列

    公开(公告)号:US07292334B1

    公开(公告)日:2007-11-06

    申请号:US11090352

    申请日:2005-03-25

    IPC分类号: G01J3/44

    CPC分类号: G01N21/658

    摘要: A nano-enhanced Raman scattering (NERS)-active structure includes a substrate, a monolayer of nanoparticles disposed on a surface of the substrate, and a spacer material surrounding each nanoparticle in the monolayer of nanoparticles. The monolayer of nanoparticles includes a first plurality of nanoparticles and a second plurality of nanoparticles. The nanoparticles of the second plurality are interspersed among the first plurality and exhibit a plasmon frequency that differs from any plasmon frequency exhibited by the first plurality. Also described are a method for forming such a NERS-active structure and a NERS system that includes a NERS-active structure, an excitation radiation source, and a detector for detecting Raman scattered radiation.

    摘要翻译: 纳米增强拉曼散射(NERS)活性结构包括底物,设置在基底表面上的单层纳米颗粒,以及围绕纳米颗粒单层中的每个纳米颗粒的间隔物。 纳米颗粒的单层包括第一多个纳米颗粒和第二多个纳米颗粒。 第二多个纳米颗粒散布在第一多个中,并且表现出与第一多个表现出的任何等离子体频率不同的等离子体激元频率。 还描述了形成这样的NERS-活性结构的方法和包括NERS-活性结构,激发辐射源和用于检测拉曼散射辐射的检测器的NERS系统。

    Nanowires for surface-enhanced Raman scattering molecular sensors
    77.
    发明授权
    Nanowires for surface-enhanced Raman scattering molecular sensors 有权
    纳米线用于表面增强拉曼散射分子传感器

    公开(公告)号:US07245370B2

    公开(公告)日:2007-07-17

    申请号:US11030733

    申请日:2005-01-06

    IPC分类号: G01J3/44 G01N21/65

    CPC分类号: G01N21/658

    摘要: A SERS-active structure is disclosed that includes a substrate and at least two nanowires disposed on the substrate. Each of the at least two nanowires has a first end and a second end, the first end being attached to the substrate and the second end having a SERS-active tip. A SERS system is also disclosed that includes a SERS-active structure. Also disclosed are methods for forming a SERS-active structure and methods for performing SERS with SERS-active structures.

    摘要翻译: 公开了一种SERS-活性结构,其包括衬底和设置在衬底上的至少两个纳米线。 所述至少两个纳米线中的每一个具有第一端和第二端,所述第一端附接到所述基底,所述第二端具有SERS活性末端。 还公开了包括SERS活性结构的SERS系统。 还公开了形成SERS活性结构的方法和用SERS活性结构进行SERS的方法。

    Integrated circuit substrate that accommodates lattice mismatch stress
    78.
    发明授权
    Integrated circuit substrate that accommodates lattice mismatch stress 有权
    集成电路基板,适应晶格失配应力

    公开(公告)号:US06429466B2

    公开(公告)日:2002-08-06

    申请号:US09774199

    申请日:2001-01-29

    IPC分类号: H01L31072

    摘要: A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The second material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the first material by the second material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates. In the case of silicon-based substrates, the buried layer is preferably SiO2 that is sufficiently malleable at the growth temperature to allow the deformation of the isolated substrate layer.

    摘要翻译: 一种用于生长晶体层的方法,其包括在第二材料的晶体衬底的生长表面上的第一材料,其中第一材料和第二材料具有不同的晶格常数。 在衬底中产生掩埋层,使得掩埋层将衬底的包含生长表面的衬底与衬底的其余部分隔离。 然后将第二种材料在生长温度下沉积在生长表面上。 衬底的隔离层的厚度小于在其上结晶第二材料时在第一材料的晶格中产生缺陷的厚度。 掩埋层在生长温度下具有足够的延展性,以允许隔离层的晶格变形,而不使基底的其余部分变形。 本发明可用于在硅衬底上生长III-V半导体材料层。 在硅基基板的情况下,掩埋层优选是在生长温度下足够有韧性的SiO 2,以允许隔离的基底层的变形。

    Fabricating a semiconductor device with strained Si.sub.1-x Ge.sub.x
layer
    79.
    发明授权
    Fabricating a semiconductor device with strained Si.sub.1-x Ge.sub.x layer 失效
    制造具有应变Si1-xGex层的半导体器件

    公开(公告)号:US5256550A

    公开(公告)日:1993-10-26

    申请号:US715054

    申请日:1991-06-12

    IPC分类号: H01L21/20 H01L21/205

    摘要: The present invention comprises a method of fabricating devices and circuits employing at least one heteroepitaxial layer under strain. The thickness of the heteroepitaxial layer is more than two times the calculated equilibrium critical thickness for an uncapped heteroepitaxial layer upon a crystalline substrate, based on previously known equilibrium theory for the uncapped layer. Subsequent to growth of the heteroepitaxial layer, the structure is processed at temperatures higher than the growth temperature of the heteroepitaxial layer.The strained heteroepitaxial layer (second layer) is epitaxially grown upon the surface of a first, underlaying crystalline layer, creating a heterojunction. Subsequently a third crystalline layer is deposited or grown upon the major exposed surface of the second, strained heteroepitaxial layer. The preferred manner of growth of the third crystalline layer is epitaxial growth. The composition of the third crystalline layer must be such that upon deposition or growth, the third layer substantially continuously binds to the heteroepitaxial structure of the second layer. Subsequent to growth of the at least three layer structure, the structure is processed at temperatures in excess of the growth temperature of the second heteroepitaxial layer. Presence of the third crystalline layer prevents the generation of a substantial amount of misfit dislocations between the first crystalline layer substrate and the second heteroepitaxial layer.

    摘要翻译: 本发明包括一种在应变下使用至少一个异质外延层的器件和电路的制造方法。 基于先前已知的无盖层的平衡理论,异质外延层的厚度超过了在结晶衬底上的无盖异质外延层的计算的平衡临界厚度的两倍。 在异质外延层的生长之后,在高于异质外延层的生长温度的温度下处理该结构。 应变异质外延层(第二层)在第一底层晶体层的表面上外延生长,产生异质结。 随后,在第二应变异质外延层的主要暴露表面上沉积或生长第三晶体层。 第三晶体层的优选生长方式是外延生长。 第三结晶层的组成必须使得在沉积或生长时,第三层基本上连续地结合到第二层的异质外延结构。 在至少三层结构生长之后,在超过第二异质外延层的生长温度的温度下处理该结构。 第三结晶层的存在防止在第一晶体层衬底和第二异质外延层之间产生大量的失配位错。

    Bipolar transistor structure with reduced collector-to-substrate
capacitance
    80.
    发明授权
    Bipolar transistor structure with reduced collector-to-substrate capacitance 失效
    具有降低的集电极到基板电容的双极晶体管结构

    公开(公告)号:US5252143A

    公开(公告)日:1993-10-12

    申请号:US837683

    申请日:1992-02-18

    摘要: A pre-processed substrate structure for a semiconductor device. A subcollector layer is spaced apart from a substrate by a dielectric. A relatively small, lightly-doped epitaxial feed-through layer extends through the dielectric between the substrate and the subcollector. A transistor constructed over the subcollector has very low collector-to-substrate capacitance. A plurality of devices on a common substrate are electrically isolated from each other by channel stops formed in the substrate around each device.

    摘要翻译: 一种用于半导体器件的预处理衬底结构。 子集电极层通过电介质与衬底间隔开。 相对较小的轻掺杂的外延馈通层延伸穿过衬底和子集电极之间的电介质。 在子集电极上构造的晶体管具有非常低的集电极到衬底电容。 公共衬底上的多个器件通过形成在每个器件周围的衬底中的通道停止来彼此电隔离。