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71.发明授权Method and apparatus for directory-based coherence with distributed directory management 有权基于目录的分布式目录管理一致性的方法和装置公开(公告)号：US07363432B2
公开(公告)日：2008-04-22
申请号：US10809581
申请日：2004-03-25
IPC分类号： G06F13/00
CPC分类号： G06F12/0824
摘要： A system for cache coherency comprises a memory. The memory comprises a plurality of data items and a plurality of directory information items, each data item uniquely associated with one of the plurality of directory information items. Each of the plurality of data items is configured in accordance with one of a plurality of access modes. Each of the plurality of directory information items comprises indicia of the access mode of its associated data item. A multiplexer couples to the memory and comprises a multiplex ratio. A plurality of buffers couple to the multiplexer and to the memory. The multiplex ratio is a function of the number of buffers in the plurality of buffers. A plurality of multiplexer/demultiplexers (MDMs) each uniquely couple to a different one of the plurality of buffers. A plurality of processing elements couple to the memory; each of the processing elements uniquely couples in a point-to-point connection to a different one of the plurality of MDMs. Each of the processing elements is configured to transmit a data request to its associated MDM, the data request identifying one of the plurality of data items and an access mode. The memory is configured to transmit a data response to each of the processing elements in response to a data request, the data response comprising the identified data item and its associated directory information. Each of the processing elements is further configured to receive the data response and to compare the associated directory information with the access mode of the data request and in the event that the associated directory information and the access mode of the data request are not compatible, to initiate coherence actions for the requested data item. A method for cache coherency is also provided.
摘要翻译： 用于高速缓存一致性的系统包括存储器。 存储器包括多个数据项和多个目录信息项，每个数据项与多个目录信息项之一唯一相关联。 根据多个访问模式中的一个配置多个数据项中的每一个。 多个目录信息项中的每一个包括其关联数据项的访问模式的标记。 多路复用器耦合到存储器并且包括复用比率。 多个缓冲器耦合到多路复用器和存储器。 复用比是多个缓冲器中的缓冲器的数量的函数。 多个多路复用器/解复用器（MDM）每个唯一地耦合到多个缓冲器中的不同的缓冲器。 多个处理元件耦合到存储器; 每个处理元件以点对点连接唯一地耦合到多个MDM中的不同的MDM。 每个处理元件被配置为向其相关联的MDM发送数据请求，该数据请求标识多个数据项之一以及访问模式。 存储器被配置为响应于数据请求向每个处理元件发送数据响应，数据响应包括所识别的数据项及其相关联的目录信息。 每个处理元件还被配置为接收数据响应并且将相关联的目录信息与数据请求的访问模式进行比较，并且在相关联的目录信息和数据请求的访问模式不兼容的情况下，将 启动所请求数据项的一致性操作。 还提供了一种用于高速缓存一致性的方法。
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公开(公告)号：US07321958B2
公开(公告)日：2008-01-22
申请号：US10697897
申请日：2003-10-30
IPC分类号： G06F12/08
CPC分类号： G06F12/0284 , G06F13/1652
摘要： A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.
摘要翻译： 提出了一种用于通过异构处理器共享存储器的系统，每个处理器适于处理其自己的指令集。 公共总线用于将公共存储器耦合到各种处理器。 在一个实施例中，用于多于一个处理器的高速缓存存储在共享存储器中。 在另一个实施例中，一些处理器包括映射到共享存储器池的本地存储器区域。 在另一个实施例中，包括在一个或多个处理器中的本地存储器被部分地共享，使得一些本地存储器被映射到共享存储器区域，而本地存储器中的剩余存储器对于特定处理器是专用的。
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73.发明授权公开(公告)号：US07299372B2
公开(公告)日：2007-11-20
申请号：US10912481
申请日：2004-08-05
申请人： Jeffrey Douglas Brown , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , Michael Fan Wang
发明人： Jeffrey Douglas Brown , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , Michael Fan Wang
IPC分类号： G06F1/28
CPC分类号： G06F1/3203
摘要： The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. The software is real time software, and the software also sets minimally acceptable activity control states. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.
摘要翻译： 本发明提供用于控制元件的功耗。 第一个功率控制命令由该元件的软件发出。 确定功率控制命令是否对应于由硬件定义的该元件的容许功率控制状态。 如果功率控制命令不是该元件的允许功率控制状态，则硬件将功率控制设置在比由软件发出的功率控制状态更高的水平。 该软件是实时软件，软件还设置了最低限度可接受的活动控制状态。 通过软件为芯片的不同元件定义功耗层级，其通过芯片上的任何元件或子元件提供最低功耗水平。
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公开(公告)号：US07299371B2
公开(公告)日：2007-11-20
申请号：US10912479
申请日：2004-08-05
IPC分类号： G06F1/28
CPC分类号： G06F1/3203
摘要： The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.
摘要翻译： 本发明提供用于控制元件的功耗。 第一个功率控制命令由该元件的软件发出。 确定功率控制命令是否对应于由硬件定义的该元件的容许功率控制状态。 如果功率控制命令不是该元件的允许功率控制状态，则硬件将功率控制设置在比由软件发出的功率控制状态更高的水平。 通过软件为芯片的不同元件定义功耗层级，其通过芯片上的任何元件或子元件提供最低功耗水平。
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公开(公告)号：US07243200B2
公开(公告)日：2007-07-10
申请号：US10891772
申请日：2004-07-15
IPC分类号： G06F12/00
CPC分类号： G06F13/28
摘要： A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.
摘要翻译： 提供了一种用于控制存储器访问的方法，装置和计算机程序。 直接存储器访问（DMA）单元已经在许多总线架构中变得普遍。 然而，管理有限的系统资源已成为多个DMA单元的挑战。 为了管理生成的多个命令并保留依赖关系，使用命令中的嵌入式标志或障碍命令。 这些操作然后可以控制执行命令的顺序，以便保留依赖性。
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公开(公告)号：US07103748B2
公开(公告)日：2006-09-05
申请号：US10318541
申请日：2002-12-12
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
IPC分类号： G06F12/12
CPC分类号： G06F12/1027 , G06F12/126
摘要： Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.
摘要翻译： 计算机系统中的存储器管理通过防止地址转换信息的一部分被替换为高速缓冲存储器中的其他类型的地址转换信息而被改进，该高速缓冲存储器被保留用于存储用于CPU更快速访问的这种地址转换信息。 这样，CPU可以识别存储在高速缓存中的地址转换信息的子集。
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公开(公告)号：US06981072B2
公开(公告)日：2005-12-27
申请号：US10455169
申请日：2003-06-05
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
CPC分类号： G06F13/28 , G06F12/1081
摘要： A system and a method are provided for improving memory management in a multiprocessor system. A direct memory access (DMA) operation is set up for a first processor. A DMA effective address is translated to a virtual address. The virtual address is translated to a physical address, which is used to access a memory hierarchy of the multiprocessor system.
摘要翻译： 提供了一种用于改善多处理器系统中的存储器管理的系统和方法。 为第一个处理器设置直接存储器访问（DMA）操作。 DMA有效地址转换为虚拟地址。 虚拟地址被转换为物理地址，用于访问多处理器系统的存储器层次结构。
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公开(公告)号：US09097590B2
公开(公告)日：2015-08-04
申请号：US12916922
申请日：2010-11-01
摘要： A data processing system and processor are provided for tracing thermal data via performance monitoring. A performance monitor is set into a tracing mode. Temperatures are sensed by a digital thermal sensor over a time period. The sensed temperatures are stored in a data structure and a trace of the sensed temperatures is graphically displayed.
摘要翻译： 提供了一种数据处理系统和处理器，用于通过性能监视跟踪热数据。 性能监视器设置为跟踪模式。 温度由数字热传感器在一段时间内感测到。 感测到的温度被存储在数据结构中，并且图形地显示感测到的温度的痕迹。
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公开(公告)号：US08838950B2
公开(公告)日：2014-09-16
申请号：US10601374
申请日：2003-06-23
申请人： David John Craft , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty
发明人： David John Craft , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty
CPC分类号： G06F21/53 , H04L9/3226 , H04L2209/56
摘要： The present invention provides for authenticating code and/or data and providing a protected environment for execution. The present invention provides for dynamically partitioning and un-partitioning a local store for the authentication of code or data. The local store is partitioned into an isolated and non-isolated section. Code or data is loaded into the isolated section. The code or data is authenticated in the isolated section of the local store. After authentication, the code is executed. After execution, the memory within the isolated region of the attached processor unit is erased, and the attached processor unit de-partitions the isolated section within the local store.
摘要翻译： 本发明提供了验证代码和/或数据并提供受保护的环境以供执行。 本发明提供了用于对代码或数据的认证的动态分区和分区本地存储。 本地商店被划分成一个隔离和非隔离的部分。 代码或数据被加载到隔离的部分。 代码或数据在本地存储的隔离部分进行身份验证。 认证后，执行代码。 在执行之后，附着的处理器单元的隔离区域内的存储器被擦除，并且附加的处理器单元对本地存储器内的隔离部分进行分区。
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80.发明授权Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set 失效在可选数量的监视终端和处理第二组时，停止对第一组循环的并行处理公开(公告)号：US08683185B2
公开(公告)日：2014-03-25
申请号：US12843224
申请日：2010-07-26
申请人： Brian Flachs , Charles Ray Johns , Ulrich Weigand
发明人： Brian Flachs , Charles Ray Johns , Ulrich Weigand
IPC分类号： G06F9/30
CPC分类号： G06F9/3887 , G06F8/452 , G06F9/30065 , G06F9/30076 , G06F9/3806 , G06F9/3838 , G06F9/384 , G06F9/3844 , G06F9/3853 , G06F9/3857
摘要： The illustrative embodiments comprise a method, data processing system, and computer program product having a processor unit for processing instructions with loops. A processor unit creates a first group of instructions having a first set of loops and second group of instructions having a second set of loops from the instructions. The first set of loops have a different order of parallel processing from the second set of loops. A processor unit processes the first group. The processor unit monitors terminations in the first set of loops during processing of the first group. The processor unit determines whether a number of terminations being monitored in the first set of loops is greater than a selectable number of terminations. In response to a determination that the number of terminations is greater than the selectable number of terminations, the processor unit ceases processing the first group and processes the second group.
摘要翻译： 示例性实施例包括具有用于处理具有循环的指令的处理器单元的方法，数据处理系统和计算机程序产品。 处理器单元创建具有第一组循环和第二组指令的第一组指令，其具有来自指令的第二组循环。 第一组循环与第二组循环具有不同的并行处理顺序。 处理器单元处理第一组。 处理器单元在第一组处理期间监视第一组回路中的终端。 处理器单元确定在第一组环路中正在监视的终端数量是否大于可选数量的终端。 响应于确定终端的数量大于可选择的终端数量，处理器单元停止处理第一组并处理第二组。
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