公开(公告)号：US20080253188A1

公开(公告)日：2008-10-16

申请号：US12142293

申请日：2008-06-19

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/06

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

摘要： A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by adjusting the threshold voltage level programmed in view of the data being programmed on a following programming cycle into adjacent memory cells, so that the coupling effect results in the desired target threshold voltages for the cells. In one embodiment of the present invention, memory cell coupling is compensated for by adjusting programming level of one or more memory cells of a first page a memory array to a higher or lower threshold verify target voltage given the data/programming level to be written to directly adjacent memory cells of a second page, so that coupling between the directly adjacent memory cells of the first and second pages brings the memory cells of first page to their final target programming level.

摘要翻译： 描述了非易失性存储器件和编程过程，其通过调整根据在随后的编程中编程的数据编程的阈值电压电平来补偿相邻浮动栅极或非导电浮动节点存储器单元的阈值栅极电压的耦合效应 循环进入相邻存储器单元，使得耦合效应导致单元的期望目标阈值电压。 在本发明的一个实施例中，通过将存储器阵列的第一页的一个或多个存储器单元的编程电平调整到给定要写入的数据/编程电平的较高或较低阈值验证目标电压来补偿存储器单元耦合 直接相邻的第二页的存储单元，使得第一和第二页的直接相邻的存储单元之间的耦合将第一页的存储单元带到其最终目标编程级。

公开(公告)号：US20080253185A1

公开(公告)日：2008-10-16

申请号：US12143015

申请日：2008-06-20

申请人： Raul-Adrian Cernea ,  Siu Lung Chan

发明人： Raul-Adrian Cernea ,  Siu Lung Chan

IPC分类号： G11C16/04

CPC分类号： G11C16/3427 ,  G11C16/08 ,  G11C16/3418 ,  G11C2216/14

摘要： Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.

摘要翻译： 源极偏置是由读/写电路的接地回路中的非零电阻引起的误差。 在感测期间，存储器单元的源极被电阻两端的电压降错误地偏置，并导致施加的控制栅极和漏极电压的误差。 当施加的控制栅极和漏极电压的参考点尽可能靠近存储器单元的源极时，该误差被最小化。 在一个优选实施例中，参考点位于施加源极控制信号的节点处。 当存储器阵列被组织在并行感测的存储器单元的页面中时，每个页面中的源耦合到页面源行，参考点被选择为经由复用器处于所选页面的页面源行。

公开(公告)号：US20080192539A1

公开(公告)日：2008-08-14

申请号：US11764594

申请日：2007-06-18

申请人： Jin-Hyeok Choi ,  Bong-Ryeol Lee

发明人： Jin-Hyeok Choi ,  Bong-Ryeol Lee

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C2216/14

摘要： A memory system includes a flash memory storing multi-bit data in one memory cell. A memory controller controls the flash memory to program the multi-bit data in the memory cell. The flash memory programs the multi-bit data in the memory cell in a single program operation.

摘要翻译： 存储器系统包括在一个存储单元中存储多位数据的闪速存储器。 存储器控制器控制闪存以对存储器单元中的多位数据进行编程。 闪存在单个程序操作中对存储单元中的多位数据进行编程。

公开(公告)号：US07404049B2

公开(公告)日：2008-07-22

申请号：US11123682

申请日：2005-05-06

申请人： Simone Bartoli ,  Stefano Surico ,  Davide Manfre′ ,  Donato Ferrario

发明人： Simone Bartoli ,  Stefano Surico ,  Davide Manfre′ ,  Donato Ferrario

IPC分类号： G06F12/00

CPC分类号： G06F12/04 ,  G11C16/10 ,  G11C2216/14

摘要： A method and system for managing a buffered program operation for plurality of words is described. In one aspect, the method and system include providing an internal buffer including a plurality of locations and at least one bit location for the plurality of locations. Each of the words is stored in a location of the plurality of locations. The words are associated with internal address bits for the locations. At least one of the internal address bits is at least one group address bit that corresponds to all of the words. A remaining portion of the internal address bits is associated at least one of the words. The at least one bit location stores the at least one group address bit for the words. Thus, in one aspect, the method and system include storing each of the words one of the buffer locations. The method and system also include associating the at least one group address bit with the buffer location for each of the words.

摘要翻译： 描述用于管理用于多个单词的缓冲程序操作的方法和系统。 一方面，该方法和系统包括提供包括多个位置的多个位置和至少一个位置的内部缓冲器。 每个词都存储在多个位置的位置。 这些单词与位置的内部地址位相关联。 至少一个内部地址位是与所有字对应的至少一个组地址位。 内部地址位的剩余部分与至少一个字相关联。 所述至少一个位位置存储所述字的至少一个组地址位。 因此，在一个方面，该方法和系统包括将每个单词存储在缓冲器位置之一中。 该方法和系统还包括将至少一个组地址位与每个字的缓冲器位置相关联。

公开(公告)号：US07394695B2

公开(公告)日：2008-07-01

申请号：US11511488

申请日：2006-08-29

申请人： Ken Takeuchi ,  Tomoharu Tanaka ,  Noboru Shibata

发明人： Ken Takeuchi ,  Tomoharu Tanaka ,  Noboru Shibata

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C7/1051 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3431 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5649 ,  G11C2211/565 ,  G11C2216/14

摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

摘要翻译： 具有三个以上值的数据以非易失性方式存储在存储单元中。 数据电路具有多个存储电路。 多个存储电路中的一个是锁存电路。 多个存储电路中的另一个是电容器。 锁存电路和电容器用于临时存储具有两位或更多位的程序/读数据。 如果由于泄漏引起的数据变化导致程序，则使用锁存电路来刷新由电容器保持的数据。 结果，即使使用多级数据，数据电路也不会变大。

公开(公告)号：US20080151648A1

公开(公告)日：2008-06-26

申请号：US11645043

申请日：2006-12-21

申请人： Sean S. Eilert ,  Rodney R. Rozman ,  Shekoufeh Qawami ,  Glenn Hinton

发明人： Sean S. Eilert ,  Rodney R. Rozman ,  Shekoufeh Qawami ,  Glenn Hinton

IPC分类号： G11C7/10

CPC分类号： G06F13/4239 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/14

摘要： In various embodiments, a plurality of non-volatile memory devices, such as NAND flash memory device, may be connected to a host controller device in a fanned out configuration that allows each of the plurality of memory devices to perform read and/or write operations simultaneously. Each non-volatile memory device may include high speed input circuitry and high speed output circuitry so that transfers to and from memory are not limited by the speed of the flash memory read/write interface.

摘要翻译： 在各种实施例中，诸如NAND闪存器件的多个非易失性存储器件可以以扇形输出配置连接到主机控制器设备，其允许多个存储器件中的每一个执行读取和/或写入操作 同时。 每个非易失性存储器件可以包括高速输入电路和高速输出电路，使得到存储器和从存储器的传送不受闪存读/写接口的速度的限制。

公开(公告)号：US20080137420A1

公开(公告)日：2008-06-12

申请号：US12034968

申请日：2008-02-21

申请人： Jin-Sung Park ,  Dae-Seok Byeon

发明人： Jin-Sung Park ,  Dae-Seok Byeon

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C2216/14

摘要： A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.

摘要翻译： 通过将第一数据加载到第一垫的页缓冲器中来编程闪存器件。 第二数据被加载到第二垫的页缓冲器中，同时在第一垫的第一存储块中编程第一数据。

公开(公告)号：US07385844B2

公开(公告)日：2008-06-10

申请号：US11494872

申请日：2006-07-27

申请人： Masaru Yano ,  Hideki Arakawa ,  Mototada Sakashita

发明人： Masaru Yano ,  Hideki Arakawa ,  Mototada Sakashita

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0475 ,  G11C16/0491 ,  G11C2216/14

摘要： A semiconductor device includes: a memory cell array that has a plurality of non-volatile memory cells each having a first bit and a second bit in different regions in a charge storing layer; an SRAM array (first memory unit) that stores data to be written into the memory cell array; a WR sense amplifier block (second memory unit) that stores first divided data to be written into the first bit and second divided data to be written into the second bit, the first divided data being formed by dividing the data into predetermined units, the second divided data being formed by dividing the data into predetermined units; and a control circuit that writes the second divided data into the first bit of the memory cells of the memory cell array (step S28) after writing the first divided data into the second bit of the memory cells of the memory cell array (step S22).

摘要翻译： 半导体器件包括：存储单元阵列，其具有多个非易失性存储单元，每个非易失性存储单元在电荷存储层中的不同区域中具有第一位和第二位; 存储要写入存储单元阵列的数据的SRAM阵列（第一存储器单元）; WR读出放大器块（第二存储器单元），其将要写入第一位的第一划分数据和要写入第二位的第二划分数据存储，第一划分数据通过将数据划分为预定单位形成，第二划分数据 通过将数据划分为预定单位形成分割数据; 以及将第一划分数据写入存储单元阵列的存储单元的第二位之后，将第二划分数据写入存储单元阵列的存储单元的第一位（步骤S28）的控制电路（步骤S 22）。

公开(公告)号：US20080133822A1

公开(公告)日：2008-06-05

申请号：US11633901

申请日：2006-12-05

申请人： Charles L. Saxe

发明人： Charles L. Saxe

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： H04N5/907 ,  G11C7/1075 ,  G11C16/10 ,  G11C16/32 ,  G11C2216/14

摘要： A flash memory system for an A/V player, utilizing a two-level round-robin write scheme upon N flash memory planes, enabling the A/V player to be loaded with data at a data throughput essentially N times the write throughput of one of the flash memory planes. The flash chips' memory cores and data registers, and the memory system's write buffers, can be kept fully utilized during data writing.

摘要翻译： 一种用于A / V播放器的闪存系统，在N个闪速存储器平面上利用两级循环写入方案，使A / V播放器能够以数据吞吐量基本上为N的一倍的写入吞吐量加载数据 的闪存盘。 闪存芯片的存储器内核和数据寄存器以及存储器系统的写入缓冲器可以在数据写入期间得到充分利用。

公开(公告)号：US20080123423A1

公开(公告)日：2008-05-29

申请号：US11944535

申请日：2007-11-23

申请人： Jin-Ki KIM

发明人： Jin-Ki KIM

IPC分类号： G11C16/04 ,  G11C7/00 ,  G11C8/00

CPC分类号： G06F3/061 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0679 ,  G11C5/025 ,  G11C7/1006 ,  G11C7/1033 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/12 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/107 ,  G11C2216/14 ,  G11C2216/20 ,  G11C2216/30

摘要： A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

摘要翻译： 一种具有串行数据接口和串行数据路径核心的存储器系统，用于从至少一个存储器组接收数据并将数据作为串行比特流提供给至少一个存储体。 记忆库分为两半，每半部分分为上下扇区。 每个扇区使用集成的自列解码电路并行提供与共享的二维页面缓冲器的数据。 存储器中的串行到并行数据转换器将并行数据从一半耦合到串行数据路径核心。 具有集成自列解码电路的共享二维页面缓冲器最小化每个存储体的电路和芯片面积开销，并且串行数据路径核心减少通常用于布线宽数据总线的芯片面积。 因此，与具有相同密度的单个存储体系统相比，实现多存储体系统而没有显着相应的芯片面积增加。