公开(公告)号：US20150109038A1

公开(公告)日：2015-04-23

申请号：US14562914

申请日：2014-12-08

申请人： IQ-Analog Corporation

发明人： Mikko Waltari ,  Michael Kappes ,  William Huff

IPC分类号： H03L7/091 ,  H03L7/18 ,  H03M1/06 ,  H03L7/093

CPC分类号： H03L7/091 ,  H03L7/093 ,  H03L7/097 ,  H03L7/18 ,  H03L7/1806 ,  H03L2207/10 ,  H03L2207/50 ,  H03M1/0626 ,  H03M1/0836 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1245

摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个示例。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时刻采样的模拟数据信号转换的。

公开(公告)号：US09007108B1

公开(公告)日：2015-04-14

申请号：US14562914

申请日：2014-12-08

申请人： IQ-Analog Corporation

发明人： Mikko Waltari ,  Michael Kappes ,  William Huff

IPC分类号： H03L7/06 ,  H03L7/091 ,  H03L7/093 ,  H03L7/18 ,  H03M1/06

CPC分类号： H03L7/091 ,  H03L7/093 ,  H03L7/097 ,  H03L7/18 ,  H03L7/1806 ,  H03L2207/10 ,  H03L2207/50 ,  H03M1/0626 ,  H03M1/0836 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1245

摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个例子。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时间采样的模拟数据信号转换的。

公开(公告)号：US08878577B2

公开(公告)日：2014-11-04

申请号：US14081568

申请日：2013-11-15

申请人： IQ-Analog Corporation

发明人： Mikko Waltari ,  Michael Kappes ,  William Huff

IPC分类号： H03L7/06 ,  H03L7/18 ,  H03M1/06 ,  H03M1/08 ,  H03M1/12

CPC分类号： H03L7/091 ,  H03L7/093 ,  H03L7/097 ,  H03L7/18 ,  H03L7/1806 ,  H03L2207/10 ,  H03L2207/50 ,  H03M1/0626 ,  H03M1/0836 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1245

摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个例子。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时刻采样的模拟数据信号转换的。

公开(公告)号：US08525599B2

公开(公告)日：2013-09-03

申请号：US12862476

申请日：2010-08-24

申请人： Ahmadreza Rofougaran

发明人： Ahmadreza Rofougaran

IPC分类号： H03B5/08

CPC分类号： H03L7/08 ,  H03B2201/025 ,  H03J2200/10 ,  H03L7/085 ,  H03L7/099 ,  H03L7/1806 ,  H03L2207/06

摘要： Aspects of a method and system for frequency tuning based on characterization of an oscillator are provided. A value of a first control word which controls a variable impedance of an oscillator may be determined. The determined value may be mapped to a corresponding value of a second control word which controls a variable impedance of a tuned circuit. The mapping may be based on a relationship between the variable impedance of the oscillator and the variable impedance of the tuned circuit, such as logical and/or mathematical relationship. The value of the first control word may be determined based on desired frequency of the tuned circuit and/or based on a desired impedance of the variable impedance of the tuned circuit. The tuned circuit may comprise, for example, an oscillator or a filter.

摘要翻译： 提供了基于振荡器特征的用于频率调谐的方法和系统的方面。 可以确定控制振荡器的可变阻抗的第一控制字的值。 所确定的值可以映射到控制调谐电路的可变阻抗的第二控制字的对应值。 该映射可以基于振荡器的可变阻抗和调谐电路的可变阻抗之间的关系，例如逻辑和/或数学关系。 可以基于调谐电路的期望频率和/或基于所调谐电路的可变阻抗的期望阻抗来确定第一控制字的值。 调谐电路可以包括例如振荡器或滤波器。

公开(公告)号：US08058942B2

公开(公告)日：2011-11-15

申请号：US12653093

申请日：2009-12-08

申请人： Paul Hammond ,  Jim Brown

发明人： Paul Hammond ,  Jim Brown

IPC分类号： H03B1/00

CPC分类号： H03L7/1806 ,  H03L7/1976

摘要： A phase-locked loop has a stable high frequency reference oscillator to provide a stable high frequency reference signal that has reference frequency that is a small submultiple of a generated frequency of a voltage controlled oscillator within the phase-locked loop. An adjustable output frequency feedback circuit has with a feedback divide ratio that is approximately the small submultiple and adjusts the feedback ratio such that the generated frequency of the voltage controlled oscillator is locked to a stable low frequency reference input signal. The feedback divide ratio is adjusted as a function of a required ratio change value that is a function of a current phase error of the generated frequency of a voltage controlled oscillator and the stable low frequency reference input signal and a phase error derivative. The phase error derivative is a difference of the current phase error and a previous phase error.

摘要翻译： 锁相环具有稳定的高频参考振荡器，以提供稳定的高频参考信号，其参考频率是锁相环内压控振荡器的产生频率的小微分。 可调输出频率反馈电路的反馈分频比大约是小分频，并调整反馈比，使得压控振荡器的发生频率被锁定到稳定的低频参考输入信号。 根据作为压控振荡器的发生频率的当前相位误差和稳定的低频参考输入信号和相位误差导数的函数的所需比率变化值来调整反馈分频比。 相位误差导数是当前相位误差和先前相位误差的差值。

公开(公告)号：US20110133795A1

公开(公告)日：2011-06-09

申请号：US12790242

申请日：2010-05-28

申请人： Gyu Suck KIM ,  Seong Hwan CHO ,  Woo Kon SON

发明人： Gyu Suck KIM ,  Seong Hwan CHO ,  Woo Kon SON

IPC分类号： H03L7/08

CPC分类号： H03L7/1806 ,  H03L2207/50

摘要： There is provided a digital phase-locked loop. A digital phase-locked loop according to an aspect of the invention may include: a reference phase accumulation unit outputting a reference sampling phase value; a phase detection unit detecting a phase difference signal; a digital loop filter filtering and averaging the phase difference signal from the phase detection unit; a digitally controlled oscillator generating an oscillation signal having a predetermined frequency; a DOC phase accumulation unit outputting the DCO sampling phase value, and generating a plurality of first to n-th D-FFs having the same frequency and different phases delayed in a sequential manner; and first to n-th D-FFs included in a closed loop including the phase detection unit, the digital loop filter, the digitally controlled oscillator, and the DOC phase accumulation unit, and operating according to the plurality of first to n-th clock signals from the DCO phase accumulation unit, respectively.

摘要翻译： 提供了数字锁相环。 根据本发明的一个方面的数字锁相环可以包括：参考相位累积单元，输出参考采样相位值; 检测相位差信号的相位检测单元; 数字环路滤波器对来自相位检测单元的相位差信号进行滤波和平均; 产生具有预定频率的振荡信号的数字控制振荡器; DOC相位累积单元输出DCO采样相位值，并且产生具有以相继方式延迟的相同频率和不同相位的多个第一至第n个D-FF; 以及包括在相位检测单元，数字环路滤波器，数字控制振荡器和DOC相位累积单元的闭环中的第一至第N-D-FF，并且根据多个第一至第n时钟 分别来自DCO相位累积单元的信号。

公开(公告)号：US07936221B2

公开(公告)日：2011-05-03

申请号：US11853588

申请日：2007-09-11

申请人： Roman Staszewski ,  Robert B. Staszewski ,  Fuqiang Shi

发明人： Roman Staszewski ,  Robert B. Staszewski ,  Fuqiang Shi

IPC分类号： H03L7/06

CPC分类号： H03L7/1806 ,  G06F1/04 ,  H03J1/0008 ,  H03L7/085 ,  H03L2207/50

摘要： A novel and useful apparatus for and method of spur reduction using computation spreading in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over and completed within an entire PLL reference clock period. Each computation being performed at a much higher processor clock frequency than the PLL reference clock rate. This functions to significantly reduce the per cycle current transient generated by the computations. Further, the frequency content of the current transients is at the higher processor clock frequency. This results in a significant reduction in spurs within sensitive portions of the output spectrum.

摘要翻译： 一种新颖有用的装置和使用数字锁相环（DPLL）架构中的计算扩展的杂散减少方法。 基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。 结合RCU的应用特定指令集处理器（ASIP）适于将原子操作的计算扩展到整个PLL参考时钟周期内并在整个PLL参考时钟周期内完成。 每个计算以比PLL参考时钟速率高得多的处理器时钟频率执行。 这个功能可以显着地减少由计算产生的每个周期的电流瞬变。 此外，电流瞬变的频率内容处于较高的处理器时钟频率。 这导致在输出光谱的敏感部分内杂散的显着减少。

公开(公告)号：US07917797B2

公开(公告)日：2011-03-29

申请号：US12125270

申请日：2008-05-22

申请人： Paolo Novellini ,  Silvio Cucchi ,  Giovanni Guasti

发明人： Paolo Novellini ,  Silvio Cucchi ,  Giovanni Guasti

IPC分类号： G06F1/08

CPC分类号： H03L7/1806 ,  H03L7/091 ,  H03L7/0994 ,  H03L2207/50 ,  H04J3/0691

摘要： Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors.

摘要翻译： 提供了从输入信号产生具有减小的偏移的一个或多个输出时钟信号的电路。 输入信号具有从具有与输出时钟信号的频率不同的频率的原始时钟信号的转变导出的转变。 输出时钟信号的频率是乘以输入信号的频率和整数比。 该电路包括一个累加器，一个分数相位检测器和一个环路滤波器。 累加器周期性地将数字偏移值添加到数值相位值。 从该数值相位值产生输出时钟信号。 分数相位检测器从数字相位值生成输入信号的每个转换的相应数值相位误差。 环路滤波器从相应的数值相位误差的滤波中产生数字偏移值。

公开(公告)号：US07907023B2

公开(公告)日：2011-03-15

申请号：US12475211

申请日：2009-05-29

申请人： Paul Cheng-Po Liang ,  Koji Takinami

发明人： Paul Cheng-Po Liang ,  Koji Takinami

IPC分类号： H03L7/099

CPC分类号： H03L7/0995 ,  H03L7/1806 ,  H03L7/183 ,  H03L2207/50

摘要： A phase lock loop utilizes a multiphase oscillator having a plurality of digital inputs. A plurality of DQ flip-flops, offset in time from each other generate a plurality of control signals to remove control phase information from the oscillator in digital form. A DQ flip-flop connected between any two digital inputs on the oscillator determines direction of the traveling wave. The direction and phase information address a look-up table to determine the current fractional phase of the oscillator. A divide by N circuit is used to reduce the oscillator frequency. A total phase indicator signal for the oscillator is determined using the current fractional phase. The total phase is compared to a reference phase to produce a control signal for making adjustments to the oscillator. In a feed-forward path, frequency dividers divide a high frequency signal from the oscillator to a lower desired frequency, thereby increasing phase resolution.

摘要翻译： 锁相环利用具有多个数字输入的多相振荡器。 在时间上偏移的多个DQ触发器产生多个控制信号，以数字形式从振荡器中去除控制相位信息。 连接在振荡器上的任何两个数字输入之间的DQ触发器决定行波的方向。 方向和相位信息寻址查找表以确定振荡器的当前分数相位。 使用N电路的除法来减少振荡器频率。 使用当前的分数阶段确定振荡器的总相位指示信号。 将总相位与参考相位进行比较，以产生用于调整振荡器的控制信号。 在前馈路径中，分频器将高频信号从振荡器分频到较低的期望频率，从而提高相位分辨率。

公开(公告)号：US07683722B2

公开(公告)日：2010-03-23

申请号：US11863531

申请日：2007-09-28

申请人： Ahmadreza Rofougaran

发明人： Ahmadreza Rofougaran

IPC分类号： H03L7/00

CPC分类号： H03L7/1806 ,  H03L7/0891

摘要： Aspects of a method and system for signal generation via a PLL with a DDFS feedback path are provided. In this regard, a phase difference between a reference signal and a feedback signal may be utilized to control a VCO, wherein the feedback signal is generated by a DDFS. Voltage, current and/or power levels of the generated feedback signal may be limited to a determined range of values. Moreover, the feedback signal may be based on an output of the VCO and a digital control word input to the DDFS. The digital control word may be programmatically controlled by, for example, a processor. Additionally, the control word may be determined based on a desired frequency of the generated feedback signal and a desired output frequency of the VCO. Accordingly, the DDFS may be clocked by the output of the VCO, or by a divided down version of the VCO output.

摘要翻译： 提供了通过具有DDFS反馈路径的PLL产生信号的方法和系统的方面。 在这方面，可以利用参考信号和反馈信号之间的相位差来控制VCO，其中反馈信号由DDFS产生。 产生的反馈信号的电压，电流和/或功率电平可以被限制在确定的值范围内。 此外，反馈信号可以基于VCO的输出和输入到DDFS的数字控制字。 数字控制字可以由例如处理器编程控制。 另外，可以基于产生的反馈信号的期望频率和VCO的期望输出频率来确定控制字。 因此，DDFS可以由VCO的输出或VCO输出的分频版本来计时。