公开(公告)号：US20060261861A1

公开(公告)日：2006-11-23

申请号：US11187061

申请日：2005-07-21

申请人： Ahmed Ali ,  Christopher Dillon

发明人： Ahmed Ali ,  Christopher Dillon

IPC分类号： G11C27/02

CPC分类号： G11C27/026 ,  H03M1/168 ,  H03M1/442

摘要： Signal sampler embodiments are provided for processing input signals along signal paths in response to mode-command signals. They include a follower transistor with a control terminal and a current terminal that establish at least part of a signal path. They also include a switched-capacitor network that receives signals from the current terminal in response to a first mode-command signal and that couple a selected one of a set of reference signals to the current terminal in response to a second mode-command signal. During a second mode-command signal, a bias switch is arranged to bias off the follower transistor by coupling a bias signal to the control terminal that approximates the selected reference signal. Accordingly, the amplitude of the reference signals can be increased to facilitate an increased dynamic range of the input signals without biasing the follower transistor into breakdown.

摘要翻译： 信号采样器实施例被提供用于响应于模式命令信号沿信号路径处理输入信号。 它们包括具有控制端子的跟随器晶体管和建立信号路径的至少一部分的电流端子。 它们还包括开关电容器网络，其响应于第一模式命令信号从当前终端接收信号，并且响应于第二模式命令信号将一组参考信号中的选定的一个耦合到当前终端。 在第二模式命令信号期间，偏置开关被布置成通过将偏置信号耦合到近似所选择的参考信号的控制端来偏置跟随器晶体管。 因此，可以增加参考信号的幅度以促进输入信号的增加的动态范围，而不会使跟随器晶体管击穿。

公开(公告)号：US07071863B1

公开(公告)日：2006-07-04

申请号：US11242691

申请日：2005-10-04

申请人： Sehat Sutardja ,  Farbod Aram

发明人： Sehat Sutardja ,  Farbod Aram

IPC分类号： H03M1/38 ,  H03M1/12

CPC分类号： H03M1/002 ,  H03M1/168 ,  H03M1/442

摘要： A circuit with reduced power consumption comprises first and second circuits that each have periodic active and inactive phases and that switch between the periodic active and inactive phases during operation. When the first circuit is in the active phase, the second circuit is in the inactive phase, and when the second circuit is in the active phase, the first circuit is in the inactive phase. A power supply communicates with the first and second circuits and generates first and second bias signals. The power supply selectively generates the first bias signal for the first circuit during the active phase of the first circuit, the second bias signal for the second circuit during the inactive phase of the second circuit, the second bias signal for the first circuit during the inactive phase of the first circuit, and the first bias signal for the second circuit during the active phase of the second circuit. The second bias signal is less than the first bias signal.

摘要翻译： 具有降低的功耗的电路包括第一和第二电路，每个电路具有周期性的有源和无效相位，并且在操作期间在周期性有源和非激活相之间切换。 当第一电路处于有效阶段时，第二电路处于非活动阶段，当第二电路处于有效阶段时，第一电路处于非活动阶段。 电源与第一和第二电路通信，并产生第一和第二偏置信号。 电源在第一电路的有效相位期间选择性地产生用于第一电路的第一偏置信号，在第二电路的非活动阶段期间用于第二电路的第二偏置信号，在非活动期间第一电路的第二偏置信号 第一电路的相位以及在第二电路的有效相位期间的第二电路的第一偏置信号。 第二偏置信号小于第一偏置信号。

公开(公告)号：US07034736B1

公开(公告)日：2006-04-25

申请号：US10980051

申请日：2004-11-02

申请人： Ahmed Mohamed Abdelatty Ali

发明人： Ahmed Mohamed Abdelatty Ali

IPC分类号： H03M1/44

CPC分类号： H03M1/0614 ,  H03M1/168

摘要： Differential processing systems are provided that reduce even-order harmonic energy. The reduction may be selectively converted to, for example, random noise. This effects a tradeoff for processing systems that can afford to accept some increase in noise to thereby gain the benefits of reduction in even-order harmonic energy. In one system embodiment, first and second signal portions of a differential signal are respectively processed along first and second signal paths in a first processing mode and along the second and first signal paths in a second processing mode. The modes are selected to perform the desired conversion of even-order harmonic energy. In another system embodiment, first and second signal portions of a differential signal are processed along first and second signal paths in a first processing mode and inverted versions of these signals are processed along the first and second signal paths in a second processing mode. In addition, output signals are inverted in the second processing mode.

摘要翻译： 提供降低偶次谐波能量的差分处理系统。 还原可以选择性地转换为例如随机噪声。 这对于能够承受噪声增加的处理系统产生折衷，从而获得降低偶次谐波能量的好处。 在一个系统实施例中，差分信号的第一和第二信号部分在第一处理模式中分别沿着第一和第二信号路径被处理，并且在第二处理模式中沿着第二和第一信号路径被处理。 选择这些模式以执行所需的偶次谐波能量的转换。 在另一系统实施例中，差分信号的第一和第二信号部分在第一处理模式下沿着第一和第二信号路径进行处理，并且在第二处理模式中沿着第一和第二信号路径处理这些信号的反相版本。 此外，输出信号在第二处理模式下被反转。

公开(公告)号：US20050110669A1

公开(公告)日：2005-05-26

申请号：US10904322

申请日：2004-11-04

申请人： Vineet Mishra ,  Visvesvaraya Pentakota

发明人： Vineet Mishra ,  Visvesvaraya Pentakota

IPC分类号： H03M1/16 ,  H03M1/34 ,  H03M1/12

CPC分类号： H03M1/168

摘要： An ADC implemented according to an aspect of the present invention contains a non-zero bit stage followed by a zero-bit stage. The non-zero bit stage generates a sub-code, which is used in generating a digital code corresponding to an input analog signal, and the zero-bit stage does not provide any such sub-codes. Such a feature may be attained by using a gain amplifier provided according to another aspect of the present invention. The gain amplifier contains a main-amplifier which operates as a zero bit stage, and is also used by the non-zero bit stage. The same capacitance value may be maintained between the input terminal and output terminal of the main-amplifier to implement the zero bit stage, which enables the main-amplifier to be implemented with a low gain.

摘要翻译： 根据本发明的一个方面实现的ADC包含非零位级，后面是零位级。 非零比特级产生用于产生对应于输入模拟信号的数字码的子码，零比特级不提供任何这样的子码。 这样的特征可以通过使用根据本发明的另一方面提供的增益放大器来实现。 增益放大器包含作为零位级工作的主放大器，也由非零位级使用。 可以在主放大器的输入端子和输出端子之间保持相同的电容值，以实现零位级，这使得能够以低增益实现主放大器。

公开(公告)号：US20050071829A1

公开(公告)日：2005-03-31

申请号：US10672609

申请日：2003-09-26

申请人： Patrick Bohan

发明人： Patrick Bohan

IPC分类号： G06F9/44 ,  G06F9/45 ,  H03M1/10 ,  H03M1/16

CPC分类号： H03M1/109 ,  H03M1/168

摘要： The present invention is directed to a diagnostic compiler for use with a pipeline analog-to-digital converter (ADC) having code sequences corresponding to stages thereof. In one embodiment, the diagnostic compiler includes a transition locator configured to determine transition locations for the code sequences. The diagnostic compiler also includes a characteristics indicator coupled to the transition locator and configured to provide at least one characteristic of the ADC based on the transition locations.

摘要翻译： 本发明涉及一种与具有对应于其阶段的代码序列的流水线模数转换器（ADC）一起使用的诊断编译器。 在一个实施例中，诊断编译器包括被配置为确定代码序列的转换位置的转换定位器。 诊断编译器还包括耦合到转换定位器的特征指示符，并且被配置为基于转换位置提供ADC的至少一个特性。

公开(公告)号：US06778013B1

公开(公告)日：2004-08-17

申请号：US10371780

申请日：2003-02-21

申请人： Ahmed Mohamed Abdelatty Ali

发明人： Ahmed Mohamed Abdelatty Ali

IPC分类号： H03F345

CPC分类号： H03F3/04 ,  H03F1/32 ,  H03F3/3432 ,  H03F3/45098 ,  H03F2200/453 ,  H03F2203/45451 ,  H03F2203/45458 ,  H03F2203/45461 ,  H03F2203/45504 ,  H03M1/168

摘要： Buffer amplifiers are provided with a replica current generator that supplements a buffer transistor and is configured to provide a replica current which substantially equals required load currents in the amplifier's output load. Because the current of the buffer transistor remains constant, its base-emitter voltage Vbe remains constant and the amplifier linearly reproduces the input signal Sin across the output load.

摘要翻译： 缓冲放大器配备有补充缓冲晶体管的复制电流发生器，并配置为提供基本上等于放大器输出负载中的所需负载电流的复制电流。 由于缓冲晶体管的电流保持恒定，其基极 - 发射极电压Vbe保持恒定，并且放大器在输出负载上线性地再现输入信号Sin。

公开(公告)号：US20040070917A1

公开(公告)日：2004-04-15

申请号：US10463933

申请日：2003-06-18

申请人： ANALOG DEVICES, INC.

发明人： Christopher Michalski

IPC分类号： F23Q003/00

CPC分类号： H03H19/004 ,  H03M1/08 ,  H03M1/168 ,  H03M1/442

摘要： Switched-capacitor structures are provided that reduce distortion and noise in their processed signals because they increase isolation between structural elements and ensure that selected elements are securely turned off in one mode and quickly turned on in another mode.

摘要翻译： 提供了开关电容器结构，其减少其处理的信号中的失真和噪声，因为它们增加了结构元件之间的隔离，并确保所选择的元件在一种模式下可靠地关闭并在另一种模式下快速导通。

公开(公告)号：US06570411B1

公开(公告)日：2003-05-27

申请号：US10174909

申请日：2002-06-17

申请人： Scott Gregory Bardsley ,  Ravi Kishore Kummaraguntla

发明人： Scott Gregory Bardsley ,  Ravi Kishore Kummaraguntla

IPC分类号： G11C2702

CPC分类号： G11C27/024 ,  G11C27/026 ,  H03H19/004 ,  H03M1/168 ,  H03M1/442

摘要： Switched-capacitor structures are provided that reduce distortion and noise in their processed signals because they increase isolation between structural elements and ensure that selected elements are securely and quickly turned off and on in different modes.

摘要翻译： 提供了开关电容器结构，其减少其处理信号中的失真和噪声，因为它们增加了结构元件之间的隔离，并确保所选元件在不同模式下安全快速地关闭和接通。

公开(公告)号：US06259392B1

公开(公告)日：2001-07-10

申请号：US09166813

申请日：1998-10-06

申请人： Hee-Cheol Choi ,  Kwang-Hee Lee

发明人： Hee-Cheol Choi ,  Kwang-Hee Lee

IPC分类号： H03M166

CPC分类号： H03M1/806 ,  H03M1/168

摘要： Multiplying Digital-to-Analog Converters (MDAC) multiply an analog input signal at an analog input terminal and a digital input signal at a digital input terminal to produce an analog output signal at an output terminal. The MDACs include unit capacitors and a feedback capacitor. The unit capacitors are connected to the analog input terminal during a first time interval and the unit capacitors are selectively connected to a first reference voltage, a second reference voltage or the output terminal during a second time interval in response to the digital input signal at the digital input terminal. The feedback capacitor is connected to the second reference voltage during the first time interval and to the output terminal during the second time interval.

摘要翻译： 乘法数字模拟转换器（MDAC）将模拟输入端的模拟输入信号和数字输入端的数字输入信号相乘，以在输出端产生模拟输出信号。 MDAC包括单位电容器和反馈电容器。 单元电容器在第一时间间隔期间连接到模拟输入端子，并且单元电容器响应于第二时间间隔期间的数字输入信号在第二时间间隔期间选择性地连接到第一参考电压，第二参考电压或输出端子 数字输入端子 反馈电容器在第一时间间隔期间连接到第二参考电压，并且在第二时间间隔期间连接到输出端子。

公开(公告)号：US06184809B2

公开(公告)日：2001-02-06

申请号：US09241879

申请日：1999-02-01

申请人： Paul C. Yu

发明人： Paul C. Yu

IPC分类号： H03M110

CPC分类号： H03M1/1004 ,  H03M1/0658 ,  H03M1/168

摘要： A user transparent self-calibration technique for an analog to digital converter is described. The technique can correct for capacitor mismatch error with minimal additional power consumption. This is done by generating a calibration signal, one for each capacitor whose calibration is desired. The signal is interleaved with the input signal, and digitized by alternating with the input signal digitization using capacitor arrays.

摘要翻译： 描述了用于模数转换器的用户透明自校准技术。 该技术可以以最小的附加功耗来校正电容器失配误差。 这通过产生校准信号来完成，对于需要校准的每个电容器来说，这是一个校准信号。 该信号与输入信号进行交织，并通过与使用电容器阵列的输入信号数字化交替进行数字化。