公开(公告)号：US07277245B1

公开(公告)日：2007-10-02

申请号：US11091608

申请日：2005-03-28

申请人： Farbod Aram ,  Sehat Sutardja

发明人： Farbod Aram ,  Sehat Sutardja

IPC分类号： G11B5/09 ,  G11B5/02

CPC分类号： G11B5/02 ,  G11B2005/0013

摘要： A write driver circuit for a magnetic storage medium that communicates with a write head having first and second nodes comprises a first driver circuit with an input and an output that communicates with the first node of the write head. A first charge pump communicates with said input and said output of said first driver circuit and provides additional current to said input of said first driver circuit during a first transition period between current flowing through the write head in a first direction and current flowing through the write head in a second direction. A second driver circuit with an input and an output communicates with the second node of the write head. A second charge pump communicates with said input and said output of said second driver circuit and provides additional current to said input of said second driver circuit during a second transition period between current flowing through the write head in said second direction and current flowing through the write head in said first direction.

摘要翻译： 用于与具有第一和第二节点的写入头通信的磁存储介质的写入驱动器电路包括具有与写入头的第一个节点通信的输入和输出的第一驱动器电路。 第一电荷泵与所述第一驱动器电路的所述输入端和所述输出端通信，并且在流过写入头的电流在第一方向上的电流和流经写入的电流之间的第一过渡期期间向所述第一驱动器电路的所述输入提供附加电流 朝第二个方向前进。 具有输入和输出的第二驱动器电路与写入头的第二节点通信。 第二电荷泵与所述第二驱动器电路的所述输入端和所述输出端通信，并且在所述第二方向上流经写入头的电流和流经写入的电流之间的第二过渡期期间向所述第二驱动电路的所述输入提供附加电流 朝着第一个方向前进。

公开(公告)号：US07161420B1

公开(公告)日：2007-01-09

申请号：US11292436

申请日：2005-12-02

申请人： Farbod Aram ,  Sehat Sutardja

发明人： Farbod Aram ,  Sehat Sutardja

IPC分类号： H03F1/36

CPC分类号： H03F3/005 ,  H03F1/08 ,  H03F3/211 ,  H03F3/45475 ,  H03F2200/36 ,  H03F2203/45138 ,  H03F2203/45288

摘要： An amplifier circuit comprises a first operational transconductance (OTA) having an input and an output and a second OTA having an input that communicates with an output of the first OTA. A third OTA has an input that communicates with an input of the first OTA. A fourth OTA has an input that communicates with an output of the third OTA and an output that communicates with the input of the second OTA. A switched capacitance circuit selectively couples a capacitance to at least one of the input of the third OTA and the output of third OTA.

摘要翻译： 放大器电路包括具有输入和输出的第一操作跨导（OTA）和具有与第一OTA的输出通信的输入的第二OTA。 第三个OTA具有与第一OTA的输入通信的输入。 第四OTA具有与第三OTA的输出通信的输入和与第二OTA的输入进行通信的输出。 开关电容电路选择性地将电容耦合到第三OTA的输入和第三OTA的输出中的至少一个。

公开(公告)号：US06839015B1

公开(公告)日：2005-01-04

申请号：US10313369

申请日：2002-12-06

申请人： Sehat Sutardja ,  Farbod Aram

发明人： Sehat Sutardja ,  Farbod Aram

IPC分类号： H03M1/00 ,  H03M1/06 ,  H03M1/16 ,  H03M1/44 ,  H03M1/38 ,  H03M1/12

CPC分类号： H03M1/002 ,  H03M1/0695 ,  H03M1/168 ,  H03M1/442

摘要： An analog to digital converter includes a first charging circuit that samples an input voltage during a charging phase. A first opamp has an input that communicates with the first charging circuit during an integrating phase. A first current source selectively generates a first bias current for the first opamp during the charging phase and a second bias current that is not equal to the first bias current during the integrating phase. The first bias current is less than the second bias current. The first current source can be a variable current source that selectively provides the first and second bias currents during the charging and integrating phases, respectively. Alternately, the first current source can include two current sources. Only one of the two current sources is connected to the first opamp during the integrating phase.

摘要翻译： 模数转换器包括在充电阶段期间对输入电压进行采样的第一充电电路。 第一运算放大器具有在积分阶段期间与第一充电电路通信的输入。 第一电流源在充电阶段选择性地产生用于第一运算放大器的第一偏置电流和在积分阶段期间不等于第一偏置电流的第二偏置电流。 第一偏置电流小于第二偏置电流。 第一电流源可以是可变电流源，其分别在充电和积分阶段期间选​​择性地提供第一和第二偏置电流。 或者，第一电流源可以包括两个电流源。 在整合阶段，两个电流源中只有一个与第一个运算放大器相连。

公开(公告)号：US06417725B1

公开(公告)日：2002-07-09

申请号：US09648462

申请日：2000-08-28

申请人： Farbod Aram ,  Sehat Sutardja

发明人： Farbod Aram ,  Sehat Sutardja

IPC分类号： G05F156

CPC分类号： H02M3/073 ,  H02M2003/077 ,  H03M1/12

摘要： A circuit to generate a reference voltage from a power supply based on a predetermined voltage level, the reference voltage being used by a switched capacitor analog to digital converter includes a follower connected between the power supply and a current source to output the reference voltage. An amplifier is connected in a negative feedback arrangement with the reference voltage and the predetermined voltage level so as to provide an output, and a buffer provides a buffered output based on the output of the amplifier. A low pass filter provides a filtered voltage for the follower based on the buffered output, and a charge pump, connected to the buffered output, causes current to flow to the buffered output. The input impedance of the buffer as viewed from the charge bump is low for low frequencies and higher for higher frequencies, whereas the input impendence of the filter as viewed from the charge pump is low for high frequencies and higher for lower frequencies.

摘要翻译： 一种用于基于预定电压电平从电源产生参考电压的电路，由开关电容器模数转换器使用的参考电压包括连接在电源和电流源之间以输出参考电压的跟随器。 放大器以负反馈布置与参考电压和预定电压电平连接，以提供输出，并且缓冲器基于放大器的输出提供缓冲输出。 低通滤波器基于缓冲输出为跟随器提供滤波电压，连接到缓冲输出的电荷泵使电流流向缓冲输出。 从电荷突起观察时缓冲器的输入阻抗对于低频为低，对于较高频率为较高，而从电荷泵观察的滤波器的输入阻抗对于高频为低，对于较低频率较高。

公开(公告)号：US08378750B2

公开(公告)日：2013-02-19

申请号：US13044183

申请日：2011-03-09

申请人： Sehat Sutardja ,  Farbod Aram

发明人： Sehat Sutardja ,  Farbod Aram

IPC分类号： H03F3/18 ,  H03F3/04

CPC分类号： H03F3/265 ,  H03F3/191 ,  H03F3/211 ,  H03F2203/21131

摘要： A class AB amplifier includes a first inductor having a first terminal in communication with a voltage source terminal. A first transistor has a drain terminal in communication with a second terminal of the first inductor. A second transistor has a source terminal in communication with a source terminal of the first transistor. A second inductor has a first terminal in communication with a drain terminal of the second transistor and a second terminal in communication with a reference potential. The drain terminals of the first transistor and the second transistor are capacitively coupled together.

摘要翻译： AB类放大器包括具有与电压源端子连通的第一端子的第一电感器。 第一晶体管具有与第一电感器的第二端子连通的漏极端子。 第二晶体管具有与第一晶体管的源极端子连通的源极端子。 第二电感器具有与第二晶体管的漏极端子连通的第一端子和与参考电位连通的第二端子。 第一晶体管和第二晶体管的漏极电容电容耦合在一起。

公开(公告)号：US07071863B1

公开(公告)日：2006-07-04

申请号：US11242691

申请日：2005-10-04

申请人： Sehat Sutardja ,  Farbod Aram

发明人： Sehat Sutardja ,  Farbod Aram

IPC分类号： H03M1/38 ,  H03M1/12

CPC分类号： H03M1/002 ,  H03M1/168 ,  H03M1/442

摘要： A circuit with reduced power consumption comprises first and second circuits that each have periodic active and inactive phases and that switch between the periodic active and inactive phases during operation. When the first circuit is in the active phase, the second circuit is in the inactive phase, and when the second circuit is in the active phase, the first circuit is in the inactive phase. A power supply communicates with the first and second circuits and generates first and second bias signals. The power supply selectively generates the first bias signal for the first circuit during the active phase of the first circuit, the second bias signal for the second circuit during the inactive phase of the second circuit, the second bias signal for the first circuit during the inactive phase of the first circuit, and the first bias signal for the second circuit during the active phase of the second circuit. The second bias signal is less than the first bias signal.

摘要翻译： 具有降低的功耗的电路包括第一和第二电路，每个电路具有周期性的有源和无效相位，并且在操作期间在周期性有源和非激活相之间切换。 当第一电路处于有效阶段时，第二电路处于非活动阶段，当第二电路处于有效阶段时，第一电路处于非活动阶段。 电源与第一和第二电路通信，并产生第一和第二偏置信号。 电源在第一电路的有效相位期间选择性地产生用于第一电路的第一偏置信号，在第二电路的非活动阶段期间用于第二电路的第二偏置信号，在非活动期间第一电路的第二偏置信号 第一电路的相位以及在第二电路的有效相位期间的第二电路的第一偏置信号。 第二偏置信号小于第一偏置信号。

公开(公告)号：US06974744B1

公开(公告)日：2005-12-13

申请号：US10836389

申请日：2004-04-30

申请人： Farbod Aram ,  Sehat Sutardja

发明人： Farbod Aram ,  Sehat Sutardja

IPC分类号： H01G4/012 ,  H01G4/20 ,  H01G4/38 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/08

CPC分类号： H01G4/012 ,  H01G4/38 ,  H01L23/5223 ,  H01L23/5225 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides a circuit and method for a fringing capacitor. The fringing capacitor includes at least two conductor layers spaced apart from each other. Each conductor layer includes at least two portions. The portions include odd ones alternating with even ones. Adjacent odd ones and even ones of the portions are spaced apart. The odd ones of the portions on a first one of the conductor layers are configured to substantially overlay the odd ones of the portions on an adjacent one of the conductor layers. The even ones of the portions on the first one of the conductor layers are configured to substantially overlay the even ones of the portions on the adjacent one of the conductor layers. The odd ones of the portions on the first one of the conductor layers are electrically coupled together and to the even ones of the portions on the adjacent one of the conductor layers, thereby defining a first electrode. The even ones of the portions on the first one of the conductor layers are electrically coupled together and to the odd ones of the portions on the adjacent one of the conductor layers, thereby defining a second electrode. A dielectric is interposed between the first and second electrodes. A guardband is spaced from the first and second electrodes.

摘要翻译： 本发明提供了一种边缘电容器的电路和方法。 边缘电容器包括彼此间隔开的至少两个导体层。 每个导体层包括至少两个部分。 这些部分包括与偶数交替的奇数。 相邻的奇数和相邻的部分间隔开。 第一导体层中的奇数部分被配置为基本上覆盖相邻导体层之间的奇数部分。 第一导体层中的部分中的偶数部分构造成基本覆盖相邻导体层之间的偶数部分。 第一导体层上的奇数部分电耦合在一起，并连接到相邻导体层之间的偶数部分，从而限定第一电极。 导体层中的第一层上的部分中的偶数部分电耦合在一起，并连接到相邻导体层上的奇数部分，由此限定第二电极。 电介质介于第一和第二电极之间。 防护带与第一和第二电极间隔开。

公开(公告)号：US06784050B1

公开(公告)日：2004-08-31

申请号：US10372617

申请日：2003-02-21

申请人： Farbod Aram ,  Sehat Sutardja

发明人： Farbod Aram ,  Sehat Sutardja

IPC分类号： H01L48242

CPC分类号： H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides a circuit and method for a fringing capacitor. The fringing capacitor includes at least two conductor layers spaced apart from each other. Each conductor layer includes at least two portions. The portions include odd ones alternating with even ones. Adjacent odd ones and even ones of the portions are spaced apart. The odd ones of the portions on a first one of the conductor layers are configured to substantially overlay the odd ones of the portions on an adjacent one of the conductor layers. The even ones of the portions on the first one of the conductor layers are configured to substantially overlay the even ones of the portions on the adjacent one of the conductor layers. The odd ones of the portions on the first one of the conductor layers are electrically coupled together and to the even ones of the portions on the adjacent one of the conductor layers, thereby defining a first electrode. The even ones of the portions on the first one of the conductor layers are electrically coupled together and to the odd ones of the portions on the adjacent one of the conductor layers, thereby defining a second electrode. A dielectric is interposed between the first and second electrodes. A guardband is spaced from the first and second electrodes.

摘要翻译： 本发明提供了一种边缘电容器的电路和方法。 边缘电容器包括彼此间隔开的至少两个导体层。 每个导体层包括至少两个部分。 这些部分包括与偶数交替的奇数。 相邻的奇数和相邻的部分间隔开。 第一导体层中的奇数部分被配置为基本上覆盖相邻导体层之间的奇数部分。 第一导体层中的部分中的偶数部分构造成基本覆盖相邻导体层之间的偶数部分。 第一导体层上的奇数部分电耦合在一起，并连接到相邻导体层之间的偶数部分，从而限定第一电极。 导体层中的第一层上的部分中的偶数部分电耦合在一起，并连接到相邻导体层上的奇数部分，由此限定第二电极。 电介质介于第一和第二电极之间。 防护带与第一和第二电极间隔开。

公开(公告)号：US20090140803A1

公开(公告)日：2009-06-04

申请号：US12326197

申请日：2008-12-02

申请人： Farbod Aram ,  Sehat Sutardja

发明人： Farbod Aram ,  Sehat Sutardja

IPC分类号： H03F3/68

CPC分类号： H03F1/42 ,  H03F1/26 ,  H03F3/005 ,  H03F2200/18 ,  H03F2200/36

摘要： An amplifier system includes a first amplifier stage having an input and an output. A second amplifier stage has an input and an output, the input of the second amplifier stage being connected to the output of the first amplifier stage. A transistor has a control terminal, a first terminal, and a second terminal, the first terminal of the transistor being coupled to the output of the first amplifier stage and the input of the second amplifier stage. A first capacitance has a first terminal and a second terminal, the first terminal of the first capacitance being connected to the input of the first amplifier stage, the second terminal of the first capacitance being connected to the second terminal of the transistor. A first current source to source current to amplifier system, the first current source being is connected to the output of the first amplifier stage. A second current source will sink current from the amplifier system. The second current source is connected to the second terminal of the first capacitance and the second terminal of the transistor.

摘要翻译： 放大器系统包括具有输入和输出的第一放大器级。 第二放大器级具有输入和输出，第二放大级的输入端连接到第一放大级的输出。 晶体管具有控制端子，第一端子和第二端子，晶体管的第一端子耦合到第一放大器级的输出端和第二放大器级的输入端。 第一电容具有第一端子和第二端子，第一电容的第一端子连接到第一放大器级的输入端，第一电容的第二端子连接到晶体管的第二端子。 将电流源放大到放大器系统的第一电流源，第一电流源连接到第一放大器级的输出端。 第二个电流源会从放大器系统吸收电流。 第二电流源连接到第一电容的第二端子和晶体管的第二端子。

公开(公告)号：US07417817B1

公开(公告)日：2008-08-26

申请号：US10392242

申请日：2003-03-18

申请人： Farbod Aram ,  Sehat Sutardja

发明人： Farbod Aram ,  Sehat Sutardja

IPC分类号： G11B5/09

CPC分类号： G11B5/02 ,  G11B2005/0013

摘要： A write driver circuit for a magnetic storage medium includes a first write driver sub-circuit that has an output that communicates with a first node of a write head. The first write driver circuit includes a first driver circuit and a first feedback path between the input and the output of the first driver circuit. A second write driver sub-circuit has an output that communicates with a second node of the write head. The second write driver sub-circuit includes a second driver circuit and a second feedback path between the input and the output of the second driver circuit. The write driver circuit has a substantially constant output impedance during operation, balanced differential and common mode resistances, and a substantially constant common mode voltage across the write head during operation.

摘要翻译： 用于磁存储介质的写入驱动器电路包括具有与写入头的第一节点通信的输出的第一写入驱动器子电路。 第一写入驱动器电路包括第一驱动器电路和第一驱动器电路的输入和输出之间的第一反馈路径。 第二写入驱动器子电路具有与写入头的第二节点通信的输出。 第二写入驱动器子电路包括第二驱动器电路和第二驱动器电路的输入和输出之间的第二反馈路径。 写操作电路在操作期间具有基本上恒定的输出阻抗，平衡差分和共模电阻，以及在操作期间跨写写头的基本上恒定的共模电压。