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公开(公告)号：US20240049447A1
公开(公告)日：2024-02-08
申请号：US18380660
申请日：2023-10-17
发明人： Janbo Zhang , Yu-Cheng Tung
IPC分类号： H10B12/00 , H01L21/762 , G11C5/06
CPC分类号： H10B12/31 , H01L21/76224 , G11C5/063 , H10B12/482 , H10B12/485 , H10B12/488
摘要： A semiconductor memory device includes a substrate, at least one word line, a plurality of bit lines and a plurality of insulating structures. The word line is disposed in the substrate, extends along a first direction, and includes a gate cap layer. The bit lines are disposed on the substrate and respectively extend along a second direction. The bit line crosses the word line, and includes a conductive layer. The insulating structures are disposed on the word line and respectively disposed between the bit lines. The bottom surface of the insulating structure is located in the gate cap layer. The area of the top surface of the insulating structure is larger than the area of the bottom surface of the insulating structure.
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公开(公告)号：US11895829B2
公开(公告)日：2024-02-06
申请号：US17837718
申请日：2022-06-10
发明人： Pei-Rou Jiang , Chao-Wen Lay
IPC分类号： H10B12/00
CPC分类号： H10B12/482
摘要： The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.
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公开(公告)号：US20240040775A1
公开(公告)日：2024-02-01
申请号：US18478031
申请日：2023-09-29
IPC分类号： H10B12/00
CPC分类号： H10B12/485 , H10B12/50 , H10B12/315 , H10B12/0335 , H10B12/482 , H10B12/488
摘要： A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells. Microelectronic devices, electronic systems, and additional methods are also described.
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公开(公告)号：US20240038830A1
公开(公告)日：2024-02-01
申请号：US18309126
申请日：2023-04-28
发明人： Jong-Min LEE
IPC分类号： H10B12/00
CPC分类号： H01L28/90 , H10B12/482 , H10B12/315
摘要： The semiconductor device is provided. The semiconductor device comprises a substrate; a plurality of lower electrodes on the substrate and arranged in a honeycomb structure; and a supporter connecting the plurality of lower electrodes to each other, wherein the supporter has a plurality of supporter holes defined therein, wherein each of the plurality of supporter holes exposes at least a portion of each of the plurality of lower electrodes, wherein the supporter includes: a plurality of first extensions extending in a first direction; and a plurality of second extensions extending in a second direction so as to intersect the plurality of first extensions, wherein each of the plurality of first extensions has first and second sidewalls, wherein each of the plurality of second extensions has third and fourth sidewalls, wherein each of the first to fourth sidewalls includes a convex portion and a concave portion.
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公开(公告)号：US20240032286A1
公开(公告)日：2024-01-25
申请号：US18335186
申请日：2023-06-15
发明人： Chansic Yoon , Jongmin Kim , Kiseok Lee , Junhyeok Ahn
IPC分类号： H10B12/00 , H01L29/423
CPC分类号： H10B12/488 , H10B12/315 , H10B12/485 , H10B12/482 , H01L29/42356
摘要： Provided is an integrated circuit device including a substrate that includes an active region defined by a trench isolation, a word line that extends in a first horizontal direction inside the substrate across the active region, a bit line that extends on the word line in a second horizontal direction orthogonal to the first horizontal direction, a direct contact that electrically connects the bit line to the active region, a pad that is on the active region and has a horizontal width that is greater than that of the active region, a buried contact that contacts a sidewall of the pad, and a conductive landing pad that extends on the buried contact in a vertical direction and faces the bit line in the first horizontal direction.
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公开(公告)号：US20240023324A1
公开(公告)日：2024-01-18
申请号：US18446506
申请日：2023-08-09
发明人： Chao LIN
IPC分类号： H10B12/00 , H01L23/522 , H01L23/528
CPC分类号： H10B12/488 , H10B12/05 , H10B12/482 , H01L23/5226 , H01L23/5283
摘要： A three-dimensional semiconductor structure and a method for forming the same are provided. The method includes the following operations. A stack structure in a source region and a drain region is etched to form a plurality of parallel first trenches extending in the first direction in the stack structure in the source region and the drain region, in which a plurality of semiconductor layers retained in the channel region serve as a plurality of channel body layers. The channel body layers extend in a second direction, and each includes a plurality of channel areas arranged in the second direction. A through via is formed in an end of the channel body layers in the second direction and penetrates the end. A conductive material is filled in the through via to form a grounded conductive plug.
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公开(公告)号：US20240023318A1
公开(公告)日：2024-01-18
申请号：US18319601
申请日：2023-05-18
发明人： Junhyeok Ahn
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/488 , H10B12/485 , H10B12/03
摘要： A semiconductor device includes an active region between portions of a device isolation layer on a substrate, a self-aligned pad layer on a first region of the active region, a bit line that is electrically connected to a second region of the active region, and a contact structure on a side surface of the bit line and electrically connected to the self-aligned pad layer. The self-aligned pad layer includes a pad protrusion that extends along an upper portion of a side surface of the first region of the active region, and a side of the self-aligned pad layer is in contact with the device isolation layer.
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公开(公告)号：US20240021518A1
公开(公告)日：2024-01-18
申请号：US18365154
申请日：2023-08-03
发明人： Jingwen LU
IPC分类号： H01L23/528 , H01L21/768 , H10B12/00
CPC分类号： H01L23/528 , H01L21/76877 , H10B12/482 , H10B12/488 , H10B12/03
摘要： Embodiments are a method for fabricating a semiconductor structure. The method includes: providing a substrate; etching the substrate to form bit line grooves extending along a first direction; sequentially forming a first isolation layer, a bit line metal line layer, a bit line conductive connection layer and a first insulating layer to obtain a bit line structure; etching to form a substrate of the bit line structure, and to obtain a plurality of active area structures arranged at intervals and a first groove, the bit line structure intersecting with the active area structures; filling the first groove with a second isolation layer to obtain a first structure; etching the first structure to form word line grooves extending along a direction perpendicular to the first direction; and sequentially forming a third isolation layer, a word line conductive connection layer and a second insulating layer in the word line groove.
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公开(公告)号：US11877437B2
公开(公告)日：2024-01-16
申请号：US17374578
申请日：2021-07-13
申请人： SK hynix Inc.
发明人： Beom Ho Mun , Eun Jeong Kim , Jong Kook Park , Seung Mi Lee , Ji Won Choi , Kyoung Tak Kim , Yun Hyuck Ji
IPC分类号： H10B12/00
CPC分类号： H10B12/315 , H10B12/0335 , H10B12/34 , H10B12/482
摘要： A semiconductor device includes: a semiconductor device, comprising: a bit line structure including a bit line contact plug, a bit line, and a bit line hard mask that are sequentially stacked over a substrate; a storage node contact plug that is spaced apart from the bit line structure; a conformal spacer that is positioned between the bit line and the storage node contact plug and includes a low-k material; and a seed liner that is positioned between the conformal spacer and the bit line and thinner than the conformal spacer.
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公开(公告)号：US20240014276A1
公开(公告)日：2024-01-11
申请号：US18149735
申请日：2023-01-04
发明人： Yizhi ZENG
IPC分类号： H01L29/417 , H10B12/00 , H01L29/40
CPC分类号： H01L29/41725 , H10B12/482 , H01L29/401
摘要： The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate and a contact structure. The substrate includes a shallow trench isolation (STI) structure and active structures separated by the STI structure. The contact structure includes a first contact structure and a second contact structure that are laminated, where the first contact structure covers a part of a top surface and a part of a side wall of the active structure.
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