公开(公告)号：US20210050856A1

公开(公告)日：2021-02-18

申请号：US17089387

申请日：2020-11-04

申请人： Huawei Technologies Co., Ltd.

发明人： Michael Bushman

IPC分类号： H03L7/099 ,  H03G3/00 ,  H03L7/093 ,  H03B5/12 ,  H03G3/30 ,  H03B5/06 ,  H03L5/02 ,  H03L7/08 ,  H03B5/04

摘要： The disclosure relates to technology for power supply for a voltage controller oscillator (VCO). A peak detector circuit determines the amplitude of the output for the VCO, which is compared to a reference value in an automatic gain control loop. An input voltage for the VCO is determined based on a difference between the reference value and the output of the peak detector circuit. The peak detector circuit can be implemented using parasitic bipolar devices in an integrated circuit formed in a CMOS process.

公开(公告)号：US20210044253A1

公开(公告)日：2021-02-11

申请号：US17076998

申请日：2020-10-22

申请人： QUALCOMM INCORPORATED

发明人： Yue CHAO ,  Yinghan WANG ,  Marco ZANUSO ,  Rajagopalan RANGARAJAN

IPC分类号： H03B5/12 ,  H03L7/093 ,  H03L7/08

摘要： A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.

公开(公告)号：US10911054B2

公开(公告)日：2021-02-02

申请号：US16906788

申请日：2020-06-19

申请人： Huawei International Pte. Ltd.

发明人： Theng Tee Yeo ,  Xuesong Chen ,  Rui Yu ,  Liu Supeng ,  Chao Yuan

IPC分类号： H03L7/093

摘要： A digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit is disclosed, which comprises: a DTC error compensator arranged to receive a phase offset signal being a processed output from a time-to-digital converter (TDC) circuit, the phase offset signal includes a DTC error corresponding to a phase difference between a reference clock signal processed by a DTC circuit and a feedback clock signal derived from an output signal of the ADPLL circuit. The compensator is arranged to process the phase offset signal for generating a digital signal representative of the DTC error, which is provided as an output signal. Also, the output signal is arranged to be subtracted from the phase offset signal to obtain a phase rectified signal of the phase offset signal.

公开(公告)号：US20210013888A1

公开(公告)日：2021-01-14

申请号：US16853076

申请日：2020-04-20

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： SHINWOONG KIM ,  MYOUNGGYUN KIM ,  CHULHO KIM ,  INHYO RYU ,  JAEWON CHOI ,  SANGWOOK HAN ,  HONGGUL HAN

IPC分类号： H03L7/089 ,  H03L7/087 ,  H03L7/095 ,  H03L7/093 ,  H03L7/091 ,  H03L7/099 ,  H03L7/195 ,  H03L7/14

摘要： A phase locked circuit includes an oscillator configured to generate an output clock signal, a first phase detector configured to detect a phase difference between an input clock signal and a feedback clock signal based on the output clock signal, a second phase detector having a wider phase locking range than that of the first phase detector and configured to detect the phase difference between the input clock signal and the feedback clock signal, and a charge pump controller configured to control an output current of a charge pump included in the second phase detector based on the phase difference detected by the first phase detector. When the phase difference between the input clock signal and the feedback clock signal is within the phase locking range of the first phase detector, the oscillator and the first phase detector are connected to each other.

公开(公告)号：US10862489B2

公开(公告)日：2020-12-08

申请号：US16670394

申请日：2019-10-31

申请人： Stichting IMEC Nederland

发明人： Johan van den Heuvel ,  Paul Mateman

IPC分类号： H03L7/099 ,  H03L7/093 ,  H03B5/12 ,  H03C3/09 ,  H03L1/00

摘要： A signal generator comprises (i) a first set of capacitors at least partially switchably connectable for adjusting a frequency of an oscillator as part of a phase-locked loop and (ii) a second set of capacitors comprised in one or more oscillator control subsystems. A method of controlling the signal generator comprises: (i) acquiring a frequency lock in the phase-locked loop, (ii) calculating, in conjunction with the acquiring of the frequency lock, a systematic capacitance error of the first set of capacitors due to process, voltage, and temperature variations based on the frequency of the oscillator and a switching state of the first set of capacitors, and (iii) calibrating the one or more oscillator control subsystems using the systematic capacitance error, thereby compensating for process, voltage, and temperature variations common between the first set of capacitors and the second set of capacitors.

公开(公告)号：US10862427B1

公开(公告)日：2020-12-08

申请号：US16857804

申请日：2020-04-24

申请人： Hong Kong Applied Science and Technology Research Institute Company, Limited

发明人： Tat Fu Chan

IPC分类号： H03L7/08 ,  H03L7/099 ,  H03L7/14 ,  H03C3/09 ,  H03L7/189 ,  H03L7/197 ,  H03L7/093 ,  H03L7/089

摘要： A two-point modulation Phase-Locked Loop (PLL) has a dual-input Voltage-Controlled Oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to an offset Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. The loop path through the VCO has a higher gain than the DAC path through the VCO, which has better linearity. A calibration unit divides the VCO output and counts pulses. The offset DAC has a data input and a gain input. During calibration, the data input of the DAC is set to minimum and then maximum values and VCO output pulses counted, and repeated for two values of the gain input to the DAC. From the four counts a K(DAC) calculator calculates the calibrated gain to apply to the gain input of the offset DAC.

公开(公告)号：US10855380B2

公开(公告)日：2020-12-01

申请号：US16270203

申请日：2019-02-07

申请人： Ciena Corporation

发明人： Sadok Aouini ,  Bilal Riaz ,  Naim Ben-Hamida ,  Lukas Jakober ,  Ahmad Abdo

IPC分类号： H04B10/61 ,  H04B10/572 ,  H04B10/60 ,  H03L7/23 ,  H04L7/033 ,  H03L7/099 ,  H04B10/69 ,  H04L7/00 ,  H03L7/087 ,  H03L7/093 ,  H03L7/081

摘要： Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.

公开(公告)号：US20200373927A1

公开(公告)日：2020-11-26

申请号：US15929830

申请日：2020-05-25

申请人： Jinghang Liang ,  Duncan George Elliott

发明人： Jinghang Liang ,  Duncan George Elliott

IPC分类号： H03L7/093 ,  H03L7/091 ,  H03L7/197 ,  H03L7/099

摘要： A control system method and apparatus that minimizes the difference between multiple state-derived signals, with application to frequency synthesis, is described. Existing Alias-Locked Loops (ALLs) use digital samplers in the feedback path to achieve a wide frequency lock range for high speed frequency synthesis, at the cost of one additional reference clock, compared to a Phase-Locked Loop (PLL). We propose the differential alias-locked loop (D-ALL) circuit architecture which uses only one reference clock input. In this D-ALL synthesizer architecture, two frequencies are derived from the voltage-controlled oscillator (VCO) output and are compared as the two inputs to the phase frequency detector (PFD). In contrast, a PLL or an ALL has a reference clock as one PFD input and a frequency derived from the VCO output as the other PFD input.

公开(公告)号：US10833686B2

公开(公告)日：2020-11-10

申请号：US16478385

申请日：2018-01-23

申请人： ams AG

发明人： Jia Sheng Chen ,  Gregor Schatzberger

IPC分类号： H03L7/099 ,  H03L7/093 ,  H03L7/187 ,  H03L7/10 ,  H03K3/03

摘要： The PLL circuit comprises a phase/frequency detector (302), a loop filter (304, 306), a VCO (308) and a feedback loop (320). The VCO can be electrically disconnected from the PLL and comprises a programmable trimming circuit (316) and a current-controlled oscillator (318). For calibration the VCO is electrically disconnected from the loop filter and from the feedback loop, a constant reference voltage is applied to the voltage input (IN), a center frequency programming code (L) is applied to the trimming circuit, the center frequency programming code is iteratively adjusted until a desired center frequency is obtained, a gain programming code (K) is applied to the trimming circuit while the adjusted code is still applied, and the gain programming code is iteratively adjusted until a desired gain is obtained. Then the VCO is connected to the PLL, which is then ready for normal operation.

公开(公告)号：US20200350919A1

公开(公告)日：2020-11-05

申请号：US16401737

申请日：2019-05-02

申请人： Apple Inc.

发明人： Cristian Marcu ,  Feng Zhao ,  Wei Deng ,  Chunwei Chang ,  Robert K. Kong ,  Saeed Chehrazi

IPC分类号： H03L7/18 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099

摘要： In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.