公开(公告)号：US09478570B2

公开(公告)日：2016-10-25

申请号：US14929077

申请日：2015-10-30

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Robert Manouvrier ,  Pascal Fonteneau ,  Xavier Montagner

IPC: H01L27/146 ,  H01L29/423

CPC classification number: H01L27/14614 ,  H01L27/14607 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689 ,  H01L29/4236

Abstract: The present disclosure relates to a photodiode comprising: a P-conductivity type substrate region, an electric charge collecting region for collecting electric charges appearing when a rear face of the substrate region receives light, the collecting region comprising an N-conductivity type region formed deep in the substrate region, an N-conductivity type read region formed in the substrate region, and an isolated transfer gate, formed in the substrate region in a deep isolating trench extending opposite a lateral face of the N-conductivity type region, next to the read region, and arranged for receiving a gate voltage to transfer electric charges stored in the collecting region toward the read region.

公开(公告)号：US09450000B2

公开(公告)日：2016-09-20

申请号：US14462724

申请日：2014-08-19

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Michel Marty ,  Sebastien Jouan ,  Laurent Frey ,  Salim Boutami

IPC: H01L31/062 ,  H01L27/144 ,  H01L31/0232 ,  H01L27/146 ,  H01L31/107 ,  H01L29/16 ,  H01L29/49 ,  H01L29/66 ,  H01L31/101 ,  H01L31/18

CPC classification number: H01L27/1443 ,  H01L27/14625 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/16 ,  H01L29/4916 ,  H01L29/6656 ,  H01L31/02327 ,  H01L31/1016 ,  H01L31/107 ,  H01L31/1804

Abstract: A photodiode includes at least one central pad arranged on a light-receiving surface of a photodiode semiconductor substrate. The pad is made of a first material and includes lateral sidewalls surrounded by a spacer made of a second material having a different optical index than the first material. The lateral dimensions of the pad are smaller than an operating wavelength of the photodiode. Both the first and second materials are transparent to that operating wavelength. The pads and spacers are formed at a same time gate electrodes and sidewall spacers of MOS transistors are formed.

Abstract translation: 光电二极管包括布置在光电二极管半导体衬底的光接收表面上的至少一个中心衬垫。 衬垫由第一材料制成，并且包括由具有与第一材料不同的光学折射率的第二材料制成的间隔件包围的侧壁。 焊盘的横向尺寸小于光电二极管的工作波长。 第一和第二材料都对该工作波长是透明的。 焊盘和间隔物同时形成栅电极和MOS晶体管的侧壁间隔物。

公开(公告)号：US20160266647A1

公开(公告)日：2016-09-15

申请号：US14641852

申请日：2015-03-09

Applicant: STMicroelectronics SA

Inventor： Jocelyn Leheup

IPC: G06F3/01 ,  G06F3/0484 ,  G06F3/0481 ,  G01S17/88

CPC classification number: G06F3/017 ,  G01S17/08 ,  G01S17/87 ,  G01S17/88 ,  G06F3/0304 ,  G06F3/0308 ,  G06F3/0421 ,  G06F3/0484

Abstract: A system includes a time of flight (TOF) ranging sensor, and a processor coupled to the TOF ranging sensor. The processor executes an operating system commanded by an input sub-program thereof. Execution of the input sub-program causes the processor to interpret command motions sensed via the TOF ranging sensor in one of a plurality of command interpretation modes, generate commands for the operating system based on the interpreted command motions, and switch among the plurality of command interpretation modes based upon sensing of a mode switch motion via the TOF ranging sensor.

Abstract translation: 系统包括飞行时间（TOF）测距传感器，以及耦合到TOF测距传感器的处理器。 处理器执行由其输入子程序命令的操作系统。 输入子程序的执行使得处理器以多个命令解释模式之一解释通过TOF测距传感器感测的命令运动，基于解释的命令运动生成操作系统的命令，并且在多个命令之间切换 基于通过TOF测距传感器感测模式切换运动的解释模式。

公开(公告)号：US09425051B2

公开(公告)日：2016-08-23

申请号：US14270603

申请日：2014-05-06

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA

Inventor： Maud Vinet ,  Laurent Grenouillet ,  Yves Morand

IPC: H01L21/84 ,  H01L21/225 ,  H01L21/22 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8238

CPC classification number: H01L21/225 ,  H01L21/2225 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618

Abstract: The substrate is provided with a first semiconducting area partially covered by a first masking pattern to define a protected surface and an open surface. A continuous layer of silicon-germanium is deposited in non-selective manner on the first semiconducting area and on the first gate pattern. The continuous silicon-germanium layer forms an interface with the first semiconducting area. A diffusion/condensation annealing is performed to make the germanium atoms diffuse from the silicon-germanium layer to the open surface of the first semiconducting area. The masking pattern is a gate stack of the transistor or is used to define the shape of the gate stack in an electrically insulating layer so as to form a self-aligned gate stack with the source and drain areas.

Abstract translation: 衬底设置有由第一掩模图案部分地覆盖以限定受保护表面和开放表面的第一半导体区域。 以非选择性方式在第一半导体区域和第一栅极图案上沉积连续的硅 - 锗层。 连续硅 - 锗层与第一半导体区形成界面。 进行扩散/缩合退火以使锗原子从硅 - 锗层扩散到第一半导体区域的开放表面。 掩模图案是晶体管的栅极堆叠，或者用于在电绝缘层中限定栅极堆叠的形状，以便形成具有源极和漏极区域的自对准栅极堆叠。

公开(公告)号：US20160233258A1

公开(公告)日：2016-08-11

申请号：US14923799

申请日：2015-10-27

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Axel CROCHERIE ,  Jean-Pierre ODDOU ,  Stéphane ALLEGRET-MARET ,  Hugues LEININGER

IPC: H01L27/146

CPC classification number: H01L27/14621 ,  H01L27/14607 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685

Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.

Abstract translation: 包括像素阵列的彩色图像传感器形成在具有接收照明的背面的半导体层中。 绝缘导电壁从背面渗入半导体层并将像素彼此分开。 对于每个像素，彩色像素从背面渗入半导体层的厚度的5至30％，并且占据由壁限定的表面积的至少90％。 导电层从过滤器的侧壁一直延伸到壁。

公开(公告)号：US09413307B2

公开(公告)日：2016-08-09

申请号：US14734514

申请日：2015-06-09

Applicant: STMicroelectronics SA

Inventor： Laurent Chabert

IPC: H03F3/45 ,  H03F3/19 ,  H03F1/02

CPC classification number: H03F3/45282 ,  G01S7/03 ,  H03D7/1433 ,  H03D7/1458 ,  H03F1/0205 ,  H03F1/0261 ,  H03F3/19 ,  H03F3/193 ,  H03F3/3028 ,  H03F3/45076 ,  H03F3/45372 ,  H03F2200/294 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2200/91 ,  H03F2203/30015 ,  H03F2203/45081 ,  H03F2203/45112 ,  H03F2203/45154 ,  H03F2203/45288 ,  H04B1/06

Abstract: An electronic device includes a transimpedance amplifier stage having an amplifier end stage of the class AB type and a preamplifier stage coupled between an output of a frequency transposition stage and an input of the amplifier end stage. A self-biased common-mode control stage is configured to bias the preamplifier stage. The preamplifier stage is formed by a differential amplifier with an active load that is biased in response to the self-biased common-mode control stage.

Abstract translation: 电子设备包括具有类AB类型的放大器末级的跨阻放大器级和耦合在频率转置级的输出和放大器端级的输入之间的前置放大级。 自偏置共模控制级被配置为偏置前置放大器级。 前置放大器级由具有响应于自偏置共模控制级偏置的有源负载的差分放大器形成。

公开(公告)号：US20160226878A1

公开(公告)日：2016-08-04

申请号：US15026588

申请日：2014-10-17

Applicant: STMicroelectronics SA ,  STMicroelectronics (Grenoble2) SAS ,  STMicroelectronics S.r.l.

Inventor： Michael Soulie ,  Riccardo Locatelli ,  Valerio Catalano ,  Hajer Ferjani ,  Giuseppe Maruccia ,  Raffaele Guarrasi ,  Giuseppe Guarnaccia

IPC: H04L29/06

Abstract: An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.

Abstract translation: 一种装置具有被配置为存储访问活动信息的数据存储。 访问活动信息指示多个不同访问参数集中的哪一个或多个是活动的。 数据存储还被配置为存储访问定义信息，其至少为每个活动的访问参数集定义多个信道，所述信道的位置信息和与所述信道相关联的交织信息。

公开(公告)号：US09397128B2

公开(公告)日：2016-07-19

申请号：US14503460

申请日：2014-10-01

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Patrick Gros D'aillon ,  Michel Marty

IPC: H01L27/146 ,  G02B5/20 ,  G02B5/28 ,  H04N9/04

CPC classification number: H01L27/14621 ,  G02B5/20 ,  G02B5/281 ,  G02B5/286 ,  G02B5/288 ,  H01L27/14685 ,  H04N9/045

Abstract: A stack of layers defines a filter and is formed by copper on hydrogenated silicon nitride supported by a carrier. The filter includes a layer of hydrogenated silicon nitride, a layer of silicon oxide on the layer of hydrogenated silicon nitride and a layer of copper on the layer of silicon oxide. The layer of hydrogenated silicon nitride may have, in a vicinity of its upper side, a ratio of a number of silicon atoms per cubic centimeter to a number of nitrogen atoms per cubic centimeter lower than 0.8 (or even lower than 0.6), with a number of silicon-hydrogen bonds smaller than or equal to 6×1021 bonds per cubic centimeter (or even smaller than 0.5×1021 bonds per cubic centimeter). The filter further includes an additional layer of copper between the layer of hydrogenated silicon nitride and the carrier.

Abstract translation: 一叠层限定了过滤器，并由由载体支撑的氢化氮化硅上的铜形成。 滤波器包括氢化氮化硅层，氢化氮化硅层上的氧化硅层和氧化硅层上的铜层。 氢化氮化硅层可以在其上侧附近具有每立方厘米的硅原子数与每立方厘米低于0.8（或甚至低于0.6）的氮原子数的比率，其中a 硅 - 氢键的数量小于或等于每立方厘米6×1021键（或甚至小于每立方厘米0.5×1021的键）。 滤波器还包括在氢化氮化硅层和载体之间的附加的铜层。

公开(公告)号：US09391057B2

公开(公告)日：2016-07-12

申请号：US14261757

申请日：2014-04-25

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L29/74 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L27/0248 ,  H01L27/0259 ,  H01L27/0296 ,  H01L27/1207

Abstract: An integrated circuit includes first and second electronic components, a buried UTBOX insulating layer, first and second ground planes plumb with the first and second electronic components, first and second wells, first and second biasing electrodes making contact with the first and second wells and with the first and second ground planes, a third electrode making contact with the first well, a first trench isolation separating the first and third electrodes and extending through the buried insulating layer as far as into the first well, and a second trench isolation that isolates the first electrode from the first component, and that does not extend as far as the interface between the first ground plane and the first well.

Abstract translation: 集成电路包括第一和第二电子元件，埋入的UTBOX绝缘层，第一和第二接地平面与第一和第二电子元件铅垂，第一和第二阱，与第一和第二阱接触的第一和第二偏压电极以及与 所述第一和第二接地平面，与所述第一阱接触的第三电极，分隔所述第一和第三电极并延伸穿过所述埋入绝缘层的第一沟槽隔离层，并且延伸到所述第一阱中;以及第二沟槽隔离， 第一电极，并且不延伸到第一接地平面和第一阱之间的界面。

公开(公告)号：US09390786B2

公开(公告)日：2016-07-12

申请号：US14813278

申请日：2015-07-30

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Christophe Lecocq ,  Kaya Can Akyel ,  Amit Chhabra ,  Dibya Dipti

IPC: G11C11/34 ,  G11C11/417 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L27/1104

Abstract: An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively.

Abstract translation: SRAM单元由FDSOI型NMOS和PMOS晶体管形成。 掺杂阱在NMOS和PMOS晶体管的下方延伸，并通过绝缘层与其分离。 偏置电压施加到掺杂阱。 施加的偏置电压根据存储单元的状态进行调整。 例如，感测存储器单元的温度，并根据检测到的温度调整偏置电压。 偏置电压的调整被配置为使得NMOS和PMOS晶体管的阈值电压分别基本上等于n和p个目标阈值电压。