公开(公告)号：US4967314A

公开(公告)日：1990-10-30

申请号：US430924

申请日：1989-11-01

Applicant: Leo M. Higgins, III

Inventor： Leo M. Higgins, III

IPC: H05K1/11 ,  H05K3/28 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4617 ,  H05K1/113 ,  H05K3/4069 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/096 ,  H05K2203/1453 ,  H05K3/28 ,  H05K3/4038

Abstract: A high density multi-level printed wiring board having inter-level electrical connections made by via interconnect holes which are drilled or punched through only those layers of the wiring board that separate the two layers containing the conductors which are to be connected and said holes being filled with a low-resistance silver-filled conductive epoxy.

Abstract translation: 一种高密度多层印刷布线板，其具有由通孔互连孔构成的层间电连接，所述通孔互连孔仅通过布线板的那些层进行钻孔或冲孔，所述层将包含要连接的导体和所述孔的两层分离 填充了低电阻银填充导电环氧树脂。

公开(公告)号：US4959771A

公开(公告)日：1990-09-25

申请号：US407693

申请日：1989-09-14

Applicant: Joseph L. Ardini, Jr. ,  Steven Small

Inventor： Joseph L. Ardini, Jr. ,  Steven Small

IPC: G06F5/06 ,  G06F7/22 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F5/065 ,  G06F7/22

Abstract: The invention comprises a write buffer system which provides residence time information that increases the merge potential and enhances the write collapse feature of a "smart" buffer. The write buffer has multiple buffer locations for storing data received from a central processor, a data merger for merging data designated by the central processor for subsequent storage in contiguous memory locations, and a write controller for selectively writing the data from the plurality of write buffer locations to the memory. The system further includes time stamp registers in communication with the write controller for storing and updating a time signal representative of the write buffer location having most recently received data. The controller is responsive in part to the time signal, and inhibits the writing to memory of the data in the write buffer location having most recently received data since this is the location most likely to be eligible for a data merge. This feature decreases the number of interruptions to the CPU for data transfer operations.

Abstract translation: 本发明包括写缓冲器系统，其提供增加合并电位并增强“智能”缓冲器的写入折叠特征的停留时间信息。 写缓冲器具有用于存储从中央处理器接收的数据的多个缓冲器位置，用于合并由中央处理器指定的数据的数据合并器，用于在连续存储器位置中随后存储;以及写控制器，用于选择性地从多个写缓冲器中写入数据 位置到内存 该系统还包括与写入控制器通信的时间戳寄存器，用于存储和更新表示具有最近接收的数据的写入缓冲器位置的时间信号。 控制器部分地响应于时间信号，并且禁止对具有最近接收的数据的写缓冲器位置中的数据的存储器的写入，因为这是最有可能符合数据合并的位置。 此功能可减少CPU对数据传输操作的中断次数。

公开(公告)号：US4825337A

公开(公告)日：1989-04-25

申请号：US194830

申请日：1988-05-17

Applicant: Maurice S. Karpman

Inventor： Maurice S. Karpman

IPC: H05K7/20

CPC classification number: H05K7/20545

Abstract: A variable thickness intermediate cooling member adapted to be disposed between a circuit board having electronic module or packages mounted thereon and a cold plate providing thermal coupling between the cold plate and the circuit board. The intermediate cooling member is comprised of a foldable heat conductive member having a manually operable handle for moving the member between a maximum thickness circuit board engaging position to provide thermal contact, and a minimum thickness circuit board disengaging position to enable access to the circuit board.

Abstract translation: 适于设置在具有安装在其上的电子模块或封装的电路板和提供冷板和电路板之间的热耦合的冷板的可变厚度中间冷却构件。 中间冷却构件包括可折叠导热构件，其具有用于在最大厚度电路板接合位置之间移动构件以提供热接触的手动操作手柄，以及最小厚度电路板分离位置以使得能够接近电路板。

公开(公告)号：US4777594A

公开(公告)日：1988-10-11

申请号：US578872

申请日：1984-02-10

Applicant: Walter A. Jones ,  Paul R. Jones, Jr. ,  David B. Papworth

Inventor： Walter A. Jones ,  Paul R. Jones, Jr. ,  David B. Papworth

IPC: G06F9/28 ,  G06F9/22 ,  G06F9/38 ,  G06F9/42

CPC classification number: G06F9/3889 ,  G06F9/3867

Abstract: A data processing system for processing a sequence of program instructions has a pipeline structure which includes an instruction pipeline and an execution pipeline. Each of the instruction and execution pipelines has a plurality of serially operating stages. The instruction pipeline reads instructions from storage and forms therefrom address data to be employed by the execution pipeline. The execution pipeline receives the address data and uses it for referencing stored data to be employed for execution of the program instructions. A program instruction flow prediction apparatus and method employ a high speed flow prediction storage element for predicting redirection of program flow prior to the time when the instruction has been decoded. Circuitry is further provided for updating the storage element, correcting erroneous branch and/or non-branch predictions, and accommodating instructions occurring on even or odd boundaries of the normally read double word instruction. Circuitry is further provided for updating the program flow in a single execution cycle so that no disruption to normal instruction sequencing occurs.

公开(公告)号：US4750154A

公开(公告)日：1988-06-07

申请号：US629349

申请日：1984-07-10

Applicant: Brian Lefsky ,  Paul K. Rodman ,  Stephen S. Corbin

Inventor： Brian Lefsky ,  Paul K. Rodman ,  Stephen S. Corbin

IPC: G06F5/06 ,  G06F9/312 ,  G06F9/38 ,  G06F13/16 ,  G06F13/42 ,  G11C5/00

CPC classification number: G06F9/30043 ,  G06F13/1631 ,  G06F13/4234 ,  G06F5/065 ,  G06F9/3824 ,  G06F9/3826

Abstract: A memory alignment system and method are disclosed having a memory bus designed to accommodate more than one write instruction at a time and where data from different write instructions are merged together when the writes are destined for alignable locations in memory. In one embodiment, a write buffer and a comparator are configured to compare successive instructions for alignable destination addresses. In another embodiment, a content associative buffer is employed to compare the address of a write instruction with the addresses of all other stored write instructions. A variable scheduler to control the unloading of the buffer is also disclosed as is an apparatus for merging data read from memory with data awaiting transmission to memory to obtain the most up-to-date version.

Abstract translation: 公开了一种存储器对准系统和方法，其具有设计成一次容纳多于一个写指令的存储器总线，并且当写入目的地是存储器中可对准位置时，来自不同写指令的数据被合并在一起。 在一个实施例中，写缓冲器和比较器被配置为比较可对准目的地地址的连续指令。 在另一个实施例中，使用内容关联缓冲器来将写指令的地址与所有其它存储的写指令的地址进行比较。 还公开了一种用于控制缓冲器卸载的可变调度器，用于将从存储器读取的数据与等待传输到存储器的数据合并以获得最新版本的装置。

公开(公告)号：US4750112A

公开(公告)日：1988-06-07

申请号：US921834

申请日：1986-10-23

Applicant: Walter A. Jones ,  Paul R. Jones, Jr. ,  Joseph L. Ardini, Jr.

Inventor： Walter A. Jones ,  Paul R. Jones, Jr. ,  Joseph L. Ardini, Jr.

IPC: G06F9/28 ,  G06F9/22 ,  G06F9/38 ,  G06F9/42

CPC classification number: G06F9/3889 ,  G06F9/3867

Abstract: A data processing system for processing a sequence of program instructions has two independent pipelines, an instruction pipeline and an execution pipeline. Each pipeline has a plurality of serially operating stages. The instruction stages read instructions from storage and form therefrom address data to be employed by the execution pipeline. The execution pipeline receives the address data and uses it for referencing stored data to be employed for execution of the program instructions. Both pipelines operate synchronously under the control of a pipeline control unit which initiates operation of at least one stage of the execution pipeline prior to completion of the instruction pipeline for a particular instruction. Thereby operation of at least one instruction stage and one execution stage of the respective pipelines overlap for each program instruction. The instruction and execution pipelines share high speed memory. The pipeline control unit can independently control the flow of instructions through the two pipelines. This is important for operation in conjunction with a microcode storage element which allows conditional branching and subroutine operation. Circuitry also detects pipeline collisions and exception conditions and delays or inhibits operation of one or more of the pipeline stages in response thereto. Under control of the pipeline control unit, one of the independent pipelines can operate while the other is halted.

Abstract translation: 用于处理程序指令序列的数据处理系统具有两个独立的管线，指令流水线和执行流水线。 每个管道具有多个连续操作阶段。 指令级从存储器读取指令并从其中形成要由执行管线采用的地址数据。 执行流水线接收地址数据，并使用它来引用要用于执行程序指令的存储数据。 两条管线在流水线控制单元的控制下同步运行，该流水线控制单元在特定指令的指令流水线完成之前启动执行流水线的至少一级的操作。 由此，对于每个程序指令，相应管道的至少一个指令级和一个执行级的操作重叠。 指令和执行管道共享高速存储器。 管道控制单元可以独立地控制通过两条管道的指令流。 这对于允许条件分支和子程序操作的微代码存储元件的操作是重要的。 电路还检测管道冲突和异常情况，并响应于此而延迟或禁止一个或多个管线级的操作。 在管道控制单元的控制下，独立管道之一可以在另一条管道停止运行。

公开(公告)号：US4724529A

公开(公告)日：1988-02-09

申请号：US701556

申请日：1985-02-14

Applicant: Suren Irukulla ,  Bimal V. Patel

Inventor： Suren Irukulla ,  Bimal V. Patel

IPC: G06F7/537 ,  G06F7/483 ,  G06F7/49 ,  G06F7/493 ,  G06F7/52 ,  G06F7/533 ,  G06F7/535

CPC classification number: G06F7/535 ,  G06F7/49 ,  G06F7/4917 ,  G06F7/5375

Abstract: A method and apparatus for radix-.beta. non-restoring division. The division process occurs in four phases. In a first phase, the input operands are transformed to produce a divisor lying in a designated numerical range. Next, a transitional phase involves generating an initial radix-.beta. quotient digit from the transformed numerator. An iterative phase of the process generates successive partial remainders according to a recursive method. From the sign and a single radix-.beta. digit of each of these partial remainders, the process generates a radix-.beta. quotient digit. Further, a fourth phase, which may run concurrently with the transitional and iterative phases, involves accumulating successively generated quotient digits to produce a final quotient value.

Abstract translation: 基数β恢复分裂的方法和装置。 分割过程分四个阶段进行。 在第一阶段中，输入操作数被变换以产生位于指定数值范围内的除数。 接下来，过渡阶段涉及从转换的分子生成初始的基数β商数。 该过程的迭代阶段根据递归方法产生连续的部分余数。 从符号和每个这些部分余数的单个基数β数字，该过程生成基数β商数。 此外，可以与过渡和迭代阶段同时运行的第四阶段涉及累积连续生成的商数以产生最终商值。

公开(公告)号：US4718032A

公开(公告)日：1988-01-05

申请号：US701573

申请日：1985-02-14

Applicant: Suren Irukulla ,  Bimal V. Patel

Inventor： Suren Irukulla ,  Bimal V. Patel

IPC: G06F7/537 ,  G06F1/035 ,  G06F7/52 ,  G06F7/535

CPC classification number: G06F7/535 ,  G06F1/0356 ,  G06F2207/5354

Abstract: A range transformation method for transforming the normalized divisor in a division calculation to a range wherein the transformed value differs from one by no more than the quantity 2.sup.-n. The method and apparatus generate the transform multiplier value from a first high order "q" digits of the divisor and generate an out-of-range indicator signal from at least those same digits. The thus generated multiplier value is modified in response to the out-of-range indicator signal when an out-of-range condition is indicated. The apparatus employs a read-only-memory for enabling the generation of the transform multiplier value without requiring either large table look-up storage or multiplicative functions. As a result, various division methods requiring an initial transformation to provide a divisor which approaches one in value can be efficiently implemented.

Abstract translation: 一种用于将分割计算中的归一化除数变换到其中变换值与1不同于量2-n的范围的范围变换方法。 该方法和装置从除数的第一高阶“q”位生成变换乘数值，并从至少相同数字生成超范围指示信号。 当指示超出范围条件时，响应于超出范围指示符信号来修改由此产生的乘数值。 该装置采用只读存储器，以便能够生成变换乘数值，而不需要大的表查找存储或乘法函数。 结果，可以有效地实现需要初始变换以提供接近于一个值的除数的各种分割方法。

公开(公告)号：US4695968A

公开(公告)日：1987-09-22

申请号：US576364

申请日：1984-02-02

Applicant: Roderick B. Sullivan, II ,  Mahesh Doshi ,  Lorne Cooper

Inventor： Roderick B. Sullivan, II ,  Mahesh Doshi ,  Lorne Cooper

IPC: G06F17/50 ,  G06G7/48 ,  G06F15/60

CPC classification number: G06F17/5022

Abstract: A digital system simulation apparatus and method to enable a user to interactively control, during simulation, sampling of signals in the digital system whose behavior is being simulated. The behavior of the system can be approximated by recognizing and displaying the circuit element inputs and outputs. Breakpoints can also be set, interactively, during simulation, for controlling initiation and termination of the sampling process. The method and apparatus can also sample upon the Nth occurrence of a specified condition.

Abstract translation: 一种数字系统模拟装置和方法，使得用户能够在仿真期间交互地控制在其模拟行为的数字系统中的信号采样。 可以通过识别和显示电路元件的输入和输出来近似系统的行为。 在模拟期间，也可以交互地设置断点，以控制采样过程的启动和终止。 方法和装置也可以在第N次发生指定条件时进行采样。

公开(公告)号：US4675551A

公开(公告)日：1987-06-23

申请号：US835997

申请日：1986-03-04

Applicant: Alexander J. Stevenson ,  Gordon A. Ross ,  Donald C. Manson

Inventor： Alexander J. Stevenson ,  Gordon A. Ross ,  Donald C. Manson

IPC: H03K19/003 ,  H03K19/088 ,  H03K17/16 ,  H03K17/76

CPC classification number: H03K19/088 ,  H03K19/00353

Abstract: A digital logic bus termination module that is to be plugged into a TTL logic backplane bus and in which the module includes a TTL logic circuit chip package having multiple terminals including a reference terminal, input terminal and output terminal. The TTL logic circuit chip package comprises an input diode, preferably a Schottky diode connected to the input terminal thereof and forming a bus termination clamping means. The bus line is connected to the input terminal of the chip package while the bus reference line is coupled to the reference or ground terminal for the circuit chip package. The TTL logic circuit chip package has the output terminal thereof unconnected so that only the diode is in operative association with the bus. One or more resistors may also be used in parallel with the clamping diodes for impedance matching purposes.

Abstract translation: 一种数字逻辑总线终端模块，其被插入到TTL逻辑背板总线中，其中该模块包括具有多个终端的TTL逻辑电路芯片封装，该多个端子包括参考端子，输入端子和输出端子。 TTL逻辑电路芯片封装包括输入二极管，优选地连接到其输入端的肖特基二极管，并形成总线终端钳位装置。 总线线路连接到芯片封装的输入端，而总线参考线耦合到用于电路芯片封装的基准或接地端子。 TTL逻辑电路芯片封装的输出端未连接，使得只有二极管与总线可操作地相关联。 一个或多个电阻器也可以与钳位二极管并联使用，用于阻抗匹配目的。