公开(公告)号：US20140242766A1

公开(公告)日：2014-08-28

申请号：US14272944

申请日：2014-05-08

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio MASUOKA ,  Hiroki NAKAMURA

IPC分类号： H01L29/66

CPC分类号： H01L29/7827 ,  H01L21/26513 ,  H01L21/3081 ,  H01L21/823431 ,  H01L21/823487 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/78

摘要： A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact.

公开(公告)号：US08755219B2

公开(公告)日：2014-06-17

申请号：US13762940

申请日：2013-02-08

申请人： Unisantis Electronics Singapore Pte. Ltd

发明人： Fujio Masuoka ,  Shintaro Arai

IPC分类号： G11C11/412

CPC分类号： G11C11/412 ,  H01L27/11

摘要： In a loadless 4T-SRAM constituted using vertical-type transistor SGTs, a small SRAM cell area is realized. In a static memory cell constituted using four MOS transistors, the MOS transistors are SGTs formed on a bulk substrate in which the drains, gates, and sources are arranged in the vertical direction. The gates of access transistors are shared, as a word line, among a plurality of cells adjacent to one another in the horizontal direction. One contact for the word line is formed for each group of cells, thereby realizing a CMOS-type loadless 4T-SRAM with a very small memory cell area.

摘要翻译： 在使用垂直型晶体管SGT构成的无负载4T SRAM中，实现了小的SRAM单元区域。 在使用四个MOS晶体管构成的静态存储单元中，MOS晶体管是形成在大体衬底上的SGT，其中漏极，栅极和源极沿垂直方向排列。 存取晶体管的栅极作为字线在水平方向上彼此相邻的多个单元中共享。 为每组单元形成一个字线的一个接点，从而实现具有非常小的存储单元面积的CMOS型无负载4T-SRAM。

公开(公告)号：US20140151767A1

公开(公告)日：2014-06-05

申请号：US14177459

申请日：2014-02-11

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio MASUOKA ,  Hiroki NAKAMURA

IPC分类号： H01L29/78

CPC分类号： H01L29/78696 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78642 ,  H01L29/78651 ,  H01L29/78654

摘要： A method for producing a semiconductor device includes a step of forming a first insulating film around a fin-shaped silicon layer and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer; a step of implanting an impurity into upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer to form diffusion layers; and a step of forming a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad. The polysilicon gate electrode and the polysilicon gate pad have a larger width than the polysilicon gate line. After these steps follow a step of depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and the polysilicon gate line, and depositing a metal layer to form a metal gate electrode and a metal gate line, and a step of forming a contact.

摘要翻译： 一种制造半导体器件的方法包括在鳍状硅层周围形成第一绝缘膜并在鳍状硅层的上部形成柱状硅层的步骤; 将杂质注入到柱状硅层和鳍状硅层的上部以及柱状硅层的下部以形成扩散层的步骤; 以及形成多晶硅栅电极，多晶硅栅极线和多晶硅栅极焊盘的步骤。 多晶硅栅电极和多晶硅栅极焊盘的宽度大于多晶硅栅极线。 在这些步骤之后，按照沉积层间绝缘膜的步骤，曝光和蚀刻多晶硅栅电极和多晶硅栅极线，并沉积金属层以形成金属栅电极和金属栅极线，以及形成接触的步骤 。

公开(公告)号：US08735971B2

公开(公告)日：2014-05-27

申请号：US13679225

申请日：2012-11-16

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/78642 ,  H01L21/02532 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L29/0657 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78696

摘要： A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes.

摘要翻译： SGT制造方法包括：形成第一和第二鳍状硅层，形成第一绝缘膜，形成第一和第二柱状硅层的工序; 通过将杂质注入到第一和第二柱状硅层的上部，第一和第二鳍状硅层的上部以及第一和第二柱状硅层的下部形成扩散层的步骤 ; 形成栅极绝缘膜和第一和第二多晶硅栅电极的步骤; 在形成在第一和第二鳍状硅层的上部的扩散层的上部形成硅化物的步骤; 以及沉积层间绝缘膜的步骤，暴露和蚀刻第一和第二多晶硅栅电极，然后沉积金属，以及形成第一和第二金属栅电极。

公开(公告)号：US20140103408A1

公开(公告)日：2014-04-17

申请号：US14053077

申请日：2013-10-14

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio MASUOKA ,  Nozomu HARADA

IPC分类号： H01L31/0232

CPC分类号： H01L31/0232 ,  H01L27/14607 ,  H01L27/14621 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14689

摘要： In a solid-state imaging device, N regions serving as photoelectric conversion diodes are formed on outer peripheries of P regions in upper portions of island-shaped semiconductors formed on a substrate, and P+ regions connected to a pixel selection line conductive layer are formed on top layer portions of upper ends of the island-shaped semiconductors so as to adjoin the N regions and the P regions. In the P+ regions, a first P+ region has a thickness less than a second P+ region, and the second P+ region has a thickness less than a third P+ region.

摘要翻译： 在固态成像装置中，在形成于基板上的岛状半导体的上部的P区域的外周形成有用作光电转换二极管的N个区域，与像素选择线导电层连接的P +区域形成在 岛状半导体的上端的上层部分与N区和P区邻接。 在P +区域中，第一P +区域的厚度小于第二P +区域，第二P +区域的厚度小于第三P +区域。

公开(公告)号：US20140091403A1

公开(公告)日：2014-04-03

申请号：US14100496

申请日：2013-12-09

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio MASUOKA ,  Hiroki NAKAMURA

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7827 ,  H01L21/3083 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/495 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

摘要： A method for producing a semiconductor device includes a step of forming a first insulating film around a fin-shaped silicon layer and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer; a step of implanting an impurity into upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer to form diffusion layers; and a step of forming a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad. The polysilicon gate electrode and the polysilicon gate pad have a larger width than the polysilicon gate line. After these steps follow a step of depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and the polysilicon gate line, and depositing a metal layer to form a metal gate electrode and a metal gate line, and a step of forming a contact.

公开(公告)号：US20140042504A1

公开(公告)日：2014-02-13

申请号：US14061082

申请日：2013-10-23

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio MASUOKA ,  Hiroki NAKAMURA

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L21/26513 ,  H01L21/3081 ,  H01L21/823431 ,  H01L21/823487 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/78

摘要： A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact.

摘要翻译： 制造方法包括在硅衬底上形成鳍状硅层，在鳍状硅层周围形成第一绝缘膜，在鳍状硅层上形成柱状硅层; 在柱状硅层的上部形成扩散层，鳍状硅层的上部和柱状硅层的下部， 形成栅极绝缘膜，多晶硅栅极电极和多晶硅栅极布线; 在鳍状硅层的上部的扩散层的上部形成硅化物; 沉积层间绝缘膜，暴露多晶硅栅电极和多晶硅栅极布线，蚀刻多晶硅栅电极和多晶硅栅极布线，然后沉积金属以形成金属栅极电极和金属栅极布线; 并形成接触。

公开(公告)号：US20140021525A1

公开(公告)日：2014-01-23

申请号：US14033886

申请日：2013-09-23

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio MASUOKA ,  Hiroki NAKAMURA

IPC分类号： H01L29/788 ,  H01L29/66

CPC分类号： H01L29/42328 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7889

摘要： A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped floating gate arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the floating gate and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the floating gate in such a manner that an inter-polysilicon insulating film is interposed between the control gate and the floating gate. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the upper, lower, and inner side surfaces of the control gate.

摘要翻译： 包括在非易失性半导体存储器中的非易失性半导体存储晶体管包括从基板侧依次形成的源极区，沟道区和漏极区的岛状半导体，中空柱状浮栅配置成 以沟道绝缘膜插入在浮动栅极和沟道区域之间的方式围绕沟道区域的外周，并且以这样的方式围绕浮动栅极的外周布置的中空柱状控制栅极 多晶硅间绝缘膜介于控制栅极和浮栅之间的方式。 多晶硅间绝缘膜被布置成位于控制栅极的浮动栅极和上，下和内侧表面之间。

公开(公告)号：US08610202B2

公开(公告)日：2013-12-17

申请号：US12894923

申请日：2010-09-30

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/1203 ,  H01L21/823885 ,  H01L21/84 ,  H01L29/78642

摘要： There is provided a semiconductor device which has a CMOS inverter circuit and which can accomplish high-integration by configuring an inverter circuit with a columnar structural body. A semiconductor device includes a columnar structural body which is arranged on a substrate and which comprises a p-type silicon, an n-type silicon, and an oxide arranged between the p-type silicon and the n-type silicon and running in the vertical direction to the substrate, n-type high-concentration silicon layers arranged on and below the p-type silicon, p-type high-concentration silicon layers arrange on and below the n-type silicon, an insulator which surrounds the p-type silicon, the n-type silicon, and the oxide, and which serves as a gate insulator, and a conductive body which surrounds the insulator and which serves as a gate electrode.

摘要翻译： 提供了具有CMOS反相器电路的半导体器件，其可以通过配置具有柱状结构体的逆变器电路来实现高集成度。 半导体器件包括柱状结构体，其被布置在衬底上，并且包括p型硅，n型硅和布置在p型硅和n型硅之间并在垂直方向上运行的氧化物 朝向衬底的方向，配置在p型硅和p型硅以上的n型高浓度硅层，p型高浓度硅层布置在n型硅的上方和下方，围绕p型硅的绝缘体 ，n型硅和氧化物，并且其用作栅极绝缘体，以及包围绝缘体并用作栅电极的导电体。

公开(公告)号：US08609494B2

公开(公告)日：2013-12-17

申请号：US13895956

申请日：2013-05-16

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Shintaro Arai ,  Tomohiko Kudo ,  Yu Jiang ,  King-Jien Chui ,  Yisuo Li ,  Xiang Li ,  Zhixian Chen ,  Nansheng Shen ,  Vladimir Bliznetsov ,  Kavitha Devi Buddharaju ,  Navab Singh

IPC分类号： H01L29/78

CPC分类号： H01L29/66484 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/78642

摘要： The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.

摘要翻译： 半导体器件包括：平面硅层上的柱状硅层; 形成在柱状硅层的底部区域中的第一n +型硅层; 形成在柱状硅层的上部区域的第二n +型硅层; 栅极绝缘膜，形成在第一和第二n +型硅层之间的沟道区的周边; 栅电极，形成在所述栅极绝缘膜的周边，并具有第一金属 - 硅化合物层; 形成在栅电极和平面硅层之间的绝缘膜，形成在柱状硅层的上侧壁中的绝缘膜侧壁; 形成在所述平面硅层中的第二金属 - 硅化合物层; 以及形成在第二n +型硅层上的电接触。