公开(公告)号：US20150364397A1

公开(公告)日：2015-12-17

申请号：US14412445

申请日：2013-07-25

Applicant: CSMC Technologies FAB2 CO., Ltd.

Inventor： ZHEWEI WANG ,  XUELEI CHEN ,  BINBIN LIU ,  LIUCHUN GAO ,  HONGXING ZHAO ,  GUOMIN HUANG ,  LONG JIANG ,  JIBIN JIAO

IPC: H01L23/31 ,  H01L29/78 ,  H01L29/66 ,  H01L23/29 ,  H01L21/02

CPC classification number: H01L23/3171 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02271 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/53295 ,  H01L29/66568 ,  H01L29/66674 ,  H01L29/78 ,  H01L29/7801 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method of forming a passivation layer of a MOS device, and a MOS device. The method of forming a passivation layer of a MOS device includes: forming a substrate; forming a dielectric on the substrate; patterning the dielectric to expose a part of the substrate; forming a metal on the exposed part of the substrate, and the dielectric; forming a TEOS on the metal; forming a PSG on the TEOS; and forming a nitrogen silicon compound on the PSG. Therefore, the cracks problem of the passivation can be alleviated.

Abstract translation: 本发明提供一种形成MOS器件的钝化层和MOS器件的方法。 形成MOS器件的钝化层的方法包括：形成衬底; 在基板上形成电介质; 图案化所述电介质以暴露所述衬底的一部分; 在基板的暴露部分上形成金属和电介质; 在金属上形成TEOS; 在TEOS上形成PSG; 并在PSG上形成氮硅化合物。 因此，可以缓解钝化的裂纹问题。

公开(公告)号：US09153781B2

公开(公告)日：2015-10-06

申请号：US14355500

申请日：2012-10-22

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Tsung-Nten Hsu ,  Zhaoyu Yang ,  Zhiyong Zhao ,  Chunshan Lu

IPC: H01L21/311 ,  H01L45/00

CPC classification number: H01L45/1633 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1675 ,  H01L45/1683

Abstract: A manufacturing method of a resistive random access storage unit, includes: forming a resistance layer on a first metal layer having a flat surface; forming a passivation layer on the resistance layer; performing an etching process to obtain a plurality of basic units, a basic unit comprising a first metal layer, a resistance layer, and a passivation layer, which are laminated sequentially; depositing a insulating dielectric layer, and flattening the insulating dielectric layer; etching the insulating dielectric layer and the passivation layer to form contacting holes corresponded to the basic units; filling metal wires in the contacting holes; forming a second metal layer. According to the above method, a uniformly distributed resistance can be formed on a whole wafer.

Abstract translation: 一种电阻随机存取存储单元的制造方法，包括：在具有平坦表面的第一金属层上形成电阻层; 在电阻层上形成钝化层; 执行蚀刻处理以获得多个基本单元，包括依次层叠的包括第一金属层，电阻层和钝化层的基本单元; 沉积绝缘介电层，并使绝缘介电层变平; 蚀刻绝缘介电层和钝化层以形成对应于基本单元的接触孔; 在接触孔中填充金属丝; 形成第二金属层。 根据上述方法，可以在整个晶片上形成均匀分布的电阻。

公开(公告)号：US20150126014A1

公开(公告)日：2015-05-07

申请号：US14355500

申请日：2012-10-22

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Tsung-Nten Hsu ,  Zhaoyu Yang ,  Zhiyong Zhao ,  Chunshan Lu

IPC: H01L45/00

CPC classification number: H01L45/1633 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1675 ,  H01L45/1683

Abstract: A manufacturing method of a resistive random access storage unit, includes: forming a resistance layer on a first metal layer having a flat surface; forming a passivation layer on the resistance layer; performing an etching process to obtain a plurality of basic units, a basic unit comprising a first metal layer, a resistance layer, and a passivation layer, which are laminated sequentially; depositing a insulating dielectric layer, and flattening the insulating dielectric layer; etching the insulating dielectric layer and the passivation layer to form contacting holes corresponded to the basic units; filling metal wires in the contacting holes; forming a second metal layer. According to the above method, a uniformly distributed resistance can be formed on a whole wafer.

Abstract translation: 一种电阻随机存取存储单元的制造方法，包括：在具有平坦表面的第一金属层上形成电阻层; 在电阻层上形成钝化层; 执行蚀刻处理以获得多个基本单元，包括依次层叠的包括第一金属层，电阻层和钝化层的基本单元; 沉积绝缘介电层，并使绝缘介电层变平; 蚀刻绝缘介电层和钝化层以形成对应于基本单元的接触孔; 在接触孔中填充金属丝; 形成第二金属层。 根据上述方法，可以在整个晶片上形成均匀分布的电阻。

公开(公告)号：US20140293664A1

公开(公告)日：2014-10-02

申请号：US14358566

申请日：2012-11-09

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD

Inventor： Guoding Dai ,  Yue Chen ,  Xiaohui Ma ,  Hui Han ,  Renyue Ma

IPC: H02M1/42

CPC classification number: H02M1/4208 ,  H02M1/08 ,  H02M1/12 ,  H02M1/38 ,  H02M1/42 ,  H02M1/44 ,  H03K17/0412 ,  H03K17/162 ,  H03K17/615 ,  H03K17/687 ,  H03K17/6877 ,  H03K2217/0081 ,  Y02B70/12 ,  Y02P80/112

Abstract: A high-voltage heavy-current drive circuit applied in a power factor corrector, comprising a current mirroring circuit (1), a level shift circuit (3), a high-voltage pre-modulation circuit (2), a dead time control circuit (4) and a heavy-current output stage (5); the heavy-current output stage adopts a Darlington output stage structure to increase the maximum operating frequency of the drive circuit. The stabilized breakdown voltage characteristic of a voltage stabilizing diode is utilized to ensure the drive circuit operating within a safe voltage range. Adding dead time control into the level shift circuit not only prevents the momentary heavy-current from a power supply to the ground during the level conversion process, but also reduces the static power consumption of the drive circuit.

Abstract translation: 一种应用于功率因数校正器的高压大电流驱动电路，包括电流镜电路（1），电平移位电路（3），高电压预调制电路（2），死区时间控制电路 （4）和大电流输出级（5）; 大电流输出级采用达林顿输出级结构，以增加驱动电路的最大工作频率。 使用稳压二极管的稳定的击穿电压特性来确保驱动电路在安全电压范围内工作。 在电平转换电路中加入死区时间控制不仅可以防止在电平转换过程中瞬间的大电流来自地电源，而且可以降低驱动电路的静态功耗。

公开(公告)号：US20140268464A1

公开(公告)日：2014-09-18

申请号：US14357724

申请日：2012-11-09

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Guoding Dai ,  Xiaohui Ma ,  ChaoYao Xue ,  Jian Ou ,  Jing Lu

IPC: H02H9/04

CPC classification number: H02H9/04 ,  H02H7/125 ,  H02M1/32 ,  H02M1/42 ,  Y02B70/12 ,  Y02P80/112

Abstract: An output over-voltage protection circuit for power factor correction, which includes a chip external compensation network, a chip external resistor divider network, a static over-voltage detection circuit, a dynamic over-voltage detection circuit and a compare circuit; The chip external compensation network is connected between the chip external resistor divider network and the dynamic over-voltage detection circuit, the chip external compensation network converts the dynamic over-voltage signal conversion to the dynamic current signal and conveys it to the dynamic over-voltage detection circuit, the dynamic over-voltage detection circuit detects the dynamic current signal and ultimately produces the dynamic over-voltage signal (DYOVP); The dynamic over-voltage signal (DYOVP) is inputted into the compare circuit, which converts the dynamic over-voltage signal (DYOVP) into a voltage compared with a reference voltage and outputs a over-voltage control signal (OVP), so as to achieve a dynamic over-voltage protection function.

Abstract translation: 一种用于功率因数校正的输出过压保护电路，包括芯片外部补偿网络，芯片外部电阻分压网络，静态过电压检测电路，动态过电压检测电路和比较电路; 芯片外部补偿网络连接在芯片外部电阻分压网络和动态过压检测电路之间，芯片外部补偿网络将动态过电压信号转换转换为动态电流信号，并将其传送到动态过电压 检测电路，动态过电压检测电路检测动态电流信号，最终产生动态过电压信号（DYOVP）; 动态过电压信号（DYOVP）被输入到比较电路中，其将动态过电压信号（DYOVP）转换为与参考电压相比的电压，并输出过压控制信号（OVP），以便 实现动态过压保护功能。

公开(公告)号：US12249645B2

公开(公告)日：2025-03-11

申请号：US17620952

申请日：2020-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zhili Zhang ,  Jingchuan Zhao ,  Sen Zhang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method of manufacturing the LDMOS device are disclosed. The method includes: obtaining a substrate with a drift region formed thereon, the drift region having a first conductivity type and disposed on the substrate of a second conductivity type; etching the drift region to form therein a sinking structure, the sinking structure includes at least one of an implanting groove and an implanting hole; implanting ions of the second conductivity type at the bottom of the sinking structure; forming a buried layer of the second conductivity type by causing diffusion of the ions of the second conductivity type using a thermal treatment; and filling an electrical property modification material into the sinking structure, the electrical property modification material differs from the material of the drift region.

公开(公告)号：US20240304720A1

公开(公告)日：2024-09-12

申请号：US18576942

申请日：2022-12-14

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Liang SONG ,  Yongshun LI ,  Mei YUAN ,  Yanan WANG ,  Lin LUO ,  Qiang ZHANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0603 ,  H01L29/66681

Abstract: The present disclosure involves a semiconductor device and a manufacturing method thereof. A second well region is inserted between first well regions of a semiconductor device to improve the breakdown voltage of the device, and at the same time, the dimension of the upper surface of the second well region in the width direction of the device's conductive channel is set to be smaller than the dimension of the lower surface of the second well region in the width direction of the device's conductive channel to increase the dimension of the upper surface of the adjacent first well region in the width direction of the device's conductive channel. That is, the path width of the current flowing through the upper surface of the drift region is increased when the device is on, and thus the device's on-resistance is reduced.

公开(公告)号：US20240290846A1

公开(公告)日：2024-08-29

申请号：US18572595

申请日：2022-04-28

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Qun LIU ,  Song ZHANG ,  Yaohui ZHOU ,  Dejin WANG ,  Wenming ZHU

IPC: H01L29/40 ,  H01L29/45

CPC classification number: H01L29/401 ,  H01L29/456

Abstract: A forming method for a floating contact hole, and a semiconductor device. The method comprises: obtaining a substrate, and forming a tunnel oxide layer and a plurality of gates on the substrate; forming a metal silicide barrier layer; forming a self-aligned metal silicide; forming an interlayer dielectric layer; performing photoetching on the interlayer dielectric layer to obtain a photoresist pattern, the photoresist pattern comprising a small adhesive strip in the middle of the floating contact hole; and etching the floating contact hole by using the photoresist pattern as an etching mask layer.

公开(公告)号：US20240234520A9

公开(公告)日：2024-07-11

申请号：US18277658

申请日：2021-07-28

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： CHUNXU LI ,  FENG LIN ,  SHUXIAN CHEN ,  HONGFENG JIN ,  HUAJUN JIN ,  GANG HUANG ,  YU HUANG ,  BIN YANG

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/66681 ,  H01L29/7816

Abstract: A laterally diffused metal oxide semiconductor device and a preparation method thereof are disclosed. The semiconductor device includes: a substrate; a body region having a first conductivity type and formed in the substrate; a drift region, having a second conductivity type, formed in the substrate and adjacent to the body region; a field plate structure, formed on the drift region, a lower surface of an end of the field plate structure close to the body region being flush with the upper surface of the substrate, and the end of the field plate structure close to the body region also having an upwardly extending inclined surface; and a drain region, having a second conductivity type, formed in an upper layer of the drift region, and in contact with the end of the field plate structure away from the body region.

公开(公告)号：US12022270B2

公开(公告)日：2024-06-25

申请号：US17761669

申请日：2020-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jiale Su ,  Guoping Zhou ,  Xinwei Zhang ,  Changfeng Xia

IPC: H04R19/04 ,  B81C1/00 ,  H04R31/00

CPC classification number: H04R31/003 ,  B81C1/00158 ,  H04R19/04 ,  B81C2201/0105 ,  B81C2201/0116 ,  B81C2201/0133 ,  H04R2201/003

Abstract: A preparation method for a micro-electromechanical systems (MEMS) microphone includes the steps of: providing a silicon substrate having a silicon surface; forming an enclosed cavity in the silicon substrate; forming a plurality of spaced apart acoustic holes in the silicon substrate, each acoustic hole having two openings, one of which communicating with the cavity and the other one located on the silicon surface; forming a sacrificial layer on the silicon substrate, which includes a first filling portion, a second filling portion and a shielding portion; forming a polysilicon layer on the shielding portion; forming a recess in the silicon substrate on the side away from the silicon surface; and removing the first filling portion, the second filling portion and part of the shielding portion so that the recess is brought into communication with the cavity to form a back chamber, and that the polysilicon layer, the remainder of the shielding portion and the silicon substrate together delimit a hollow chamber, the hollow chamber communicating with the opening of the plurality of acoustic holes away from the cavity, completing the MEMS microphone.