公开(公告)号：US20090020805A1

公开(公告)日：2009-01-22

申请号：US11950143

申请日：2007-12-04

Applicant: Jin-Hwa Heo ,  Chul-Sung Kim ,  Bon-Young Koo ,  Ki-Hyun Hwang ,  Chang-Hyun Lee

Inventor： Jin-Hwa Heo ,  Chul-Sung Kim ,  Bon-Young Koo ,  Ki-Hyun Hwang ,  Chang-Hyun Lee

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28202 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518

Abstract: A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.

Abstract translation: 非易失性存储器件包括电荷存储层和衬底之间的电介质层。 可以减少电介质层的自由键，以减少/防止电荷通过游离键泄漏和/或被游离键捕获。 结果，可以增强非挥发性存储器件的数据保持性能和/或耐久性。

公开(公告)号：US07453736B2

公开(公告)日：2008-11-18

申请号：US11611972

申请日：2006-12-18

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/0466 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

Abstract: An electrically erasable charge trap nonvolatile memory cell has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage. The programmed electrically erasable charge trap nonvolatile memory cells may be erased by applying an erase voltage for a time interval that is sufficient to lower the threshold voltage the transistor from a program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage, but is higher than the initial threshold voltage. The time interval may be determined by repeatedly performing an endurance test using a time interval that is increased or decreased from an initial time interval, to obtain the time interval that meets an endurance specification, or allows a read to be performed successfully.

Abstract translation: 电可擦除电荷陷阱非易失性存储单元具有初始阈值电压，高于初始阈值电压的编程电压和低于编程阈值电压但高于初始阈值电压的擦除阈值电压。 可以通过施加足以将晶体管的阈值电压从编程阈值电压降低到低于编程阈值电压的擦除阈值电压的时间间隔施加擦除电压来擦除编程的电可擦除电荷陷阱非易失性存储器单元， 但高于初始阈值电压。 可以通过使用从初始时间间隔增加或减少的时间间隔重复执行耐久性测试来获得时间间隔，以获得满足耐久性规范的时间间隔，或允许成功执行读取。

公开(公告)号：US07449763B2

公开(公告)日：2008-11-11

申请号：US11530827

申请日：2006-09-11

Applicant: Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

Inventor： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC: H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  Y10S257/905

Abstract: This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.

Abstract translation: 本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。 非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。 每个器件隔离层具有突出在半导体衬底上的侧壁。 多个字线跨越器件隔离层。 隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。 浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。 形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极 顺序堆叠的图案。 然后在器件隔离层和控制栅极图案上形成导电层。 此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。

公开(公告)号：US07445994B2

公开(公告)日：2008-11-04

申请号：US11371379

申请日：2006-03-09

Applicant: Chang-Hyun Lee ,  Dong-Gun Park

Inventor： Chang-Hyun Lee ,  Dong-Gun Park

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/792

Abstract: Flash memory devices are provided including an integrated circuit substrate and a stack gate structure on the integrated circuit substrate. A trench isolation region is provided on the integrated circuit substrate adjacent the stack gate structure. A portion of the stack gate structure adjacent a trench sidewall of the trench isolation region may include a first nitrogen doped layer.

Abstract translation: 在集成电路基板上提供包括集成电路基板和堆叠栅极结构的闪存器件。 沟槽隔离区域设置在与堆叠栅极结构相邻的集成电路基板上。 与沟槽隔离区的沟槽侧壁相邻的堆叠栅极结构的一部分可以包括第一氮掺杂层。

公开(公告)号：US20080265308A1

公开(公告)日：2008-10-30

申请号：US12170976

申请日：2008-07-10

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: H01L21/28 ,  H01L29/792

CPC classification number: H01L29/7881 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

Abstract: A FinFET includes a fin that is on a substrate and extends away from the substrate. A device isolation layer is disposed on the substrate on both sides of the fin. An insulating layer is between the fin and the substrate. The insulating layer is directly connected to the device isolation layer and has a different thickness than the device isolation layer. A gate electrode crosses over the fin. A gate insulating layer is between the gate electrode and the fin. Source and drain regions are on the fins and on opposite sides of the gate electrode. Related nonvolatile memory devices that include FinFETs and methods of making FinFETs and nonvolatile memory devices are also disclosed.

Abstract translation: FinFET包括在衬底上并且远离衬底延伸的翅片。 器件隔离层设置在鳍片两侧的衬底上。 绝缘层位于散热片和基板之间。 绝缘层直接连接到器件隔离层，并且具有与器件隔离层不同的厚度。 栅电极跨过鳍。 栅极绝缘层位于栅电极和鳍之间。 源极和漏极区域位于鳍状物和栅电极的相对侧上。 还公开了包括FinFET和制造FinFET和非易失性存储器件的方法的相关非易失性存储器件。

公开(公告)号：US07443730B2

公开(公告)日：2008-10-28

申请号：US11953263

申请日：2007-12-10

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: G11C16/04

CPC classification number: G11C16/3418 ,  G11C16/3427

Abstract: A non-volatile memory device includes an array of flash memory cells therein and a voltage generator. The voltage generator is configured to generate a program voltage (Vpgm), a pass voltage (Vpass), a blocking voltage (Vblock) and a decoupling voltage (Vdcp) during a flash memory programming operation. The blocking voltage is generated at a level that inhibits inadvertent programming of an unselected memory cell(s). This voltage level of the blocking voltage is set so that Vdcp

Abstract translation: 非易失性存储器件包括其中的闪存单元阵列和电压发生器。 电压发生器被配置为在闪速存储器编程操作期间产生编程电压（Vpgm），通过电压（Vpass），阻断电压（Vblock）和去耦电压（Vdcp）。 阻塞电压产生在抑制非选择存储单元的无意编程的水平。 该阻塞电压的电压电平被设定为使得Vdcp

公开(公告)号：US07399672B2

公开(公告)日：2008-07-15

申请号：US11375983

申请日：2006-03-15

Applicant: Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

Inventor： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

IPC: H01L21/336

CPC classification number: H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

Abstract: Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

Abstract translation: 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分上形成电池绝缘层。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

公开(公告)号：US20080025392A1

公开(公告)日：2008-01-31

申请号：US11880969

申请日：2007-07-25

Applicant: Chang-Hyun Lee ,  Jae-Seok Kim ,  Seong-Joo Lee ,  Yun-Je Oh ,  Young-Hun Joo

Inventor： Chang-Hyun Lee ,  Jae-Seok Kim ,  Seong-Joo Lee ,  Yun-Je Oh ,  Young-Hun Joo

IPC: H04N7/26

CPC classification number: H04N19/86 ,  H04N19/115 ,  H04N19/124 ,  H04N19/142 ,  H04N19/61

Abstract: A method and apparatus for controlling a video encoding data rate in real-time in order to minimize performance deterioration, even when a scene change has occurred in an application field having a small number of available bits due to a low bit rate and a high frame rate. The method includes: a first step of determining whether scene change has occurred in a current frame; a second step of determining whether a number of current available bits is more than a preset reference when it is determined that the scene change has occurred; and a third step of adjusting a Quantization Parameter (QP) according to a first preset condition when it is determined that the number of current available bits is more than that preset reference. An apparatus includes an encoder QP controller having a QP module for adjusting the QP.

Abstract translation: 即使当由于低比特率和高帧而在具有少量可用比特的应用领域中发生场景变化时，也可以实时地控制视频编码数据速率以便最小化性能劣化的方法和装置 率。 该方法包括：确定在当前帧中是否发生场景变化的第一步骤; 当确定出现场景变化时，确定当前可用位数是否大于预设参考值的第二步骤; 以及当确定当前可用位的数量大于该预设参考值时，根据第一预设条件调整量化参数（QP）的第三步骤。 一种装置包括具有用于调整QP的QP模块的编码器QP控制器。

公开(公告)号：US07218863B2

公开(公告)日：2007-05-15

申请号：US10638453

申请日：2003-08-11

Applicant: Chang-Hyun Lee ,  Chan-Yul Kim ,  Yun-Je Oh ,  Jun-Ho Koh

Inventor： Chang-Hyun Lee ,  Chan-Yul Kim ,  Yun-Je Oh ,  Jun-Ho Koh

IPC: H04B10/04

CPC classification number: H04B10/504 ,  H04B10/58

Abstract: An optical transmission system for optimizing the bias of a laser diode during an SCM analog optical transmission includes an optical transmitter for converting a baseband electric signal into an optical signal using a laser diode according to the set bias and outputting the optical signal through an optical line, an optical receiver for converting the optical signal transmitted from the optical transmitter into the baseband electric signal, a recovery unit for detecting an error generated according to the bias of the laser diode on the basis of the electric signal converted by the optical receiver, and a bias adjuster for optimally adjusting the bias of the laser diode on the basis of a value of the error detected by the reproducer.

Abstract translation: 一种用于在SCM模拟光传输期间优化激光二极管的偏置的光传输系统包括：光发射机，用于根据设定的偏置，使用激光二极管将基带电信号转换为光信号，并通过光线路输出光信号 用于将从光发送器发送的光信号转换为基带电信号的光接收器，用于根据由光接收器转换的电信号来检测根据激光二极管的偏置产生的误差的恢复单元;以及 偏置调节器，用于基于由再现器检测到的误差的值来最佳地调整激光二极管的偏置。

公开(公告)号：US07157762B2

公开(公告)日：2007-01-02

申请号：US10982580

申请日：2004-11-04

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: H01L27/108 ,  H01L21/336

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42324

Abstract: Semiconductor devices are provided on a substrate having a cell array region and a peripheral circuit region. A first device isolation layer defines a cell active region in the cell array region and a second device isolation layer having first and second sidewalls defines a peripheral active region in the peripheral circuit region. A cell gate pattern that includes a plurality of conductive layers crosses over the cell active region, and a peripheral gate pattern that includes a plurality of conductive layers crosses over the peripheral active region. A lowermost layer of the peripheral gate pattern has first and second sidewalls that are aligned with respective of either the first and second sidewalls of the second device isolation layer or a vertical extension of the first and second sidewalls of the second device isolation layer. Further, the lowest layer of the cell gate pattern and the lowest layer of the peripheral gate pattern comprise different conductive layers.

Abstract translation: 半导体器件设置在具有单元阵列区域和外围电路区域的基板上。 第一器件隔离层限定电池阵列区域中的电池有源区，并且具有第一和第二侧壁的第二器件隔离层限定外围电路区域中的外围有源区。 包括多个导电层的单元栅极图案与单元有源区交叉，并且包括多个导电层的外围栅极图案跨过周边有源区。 外围栅极图案的最下层具有与第二器件隔离层的第一和第二侧壁的相应的第一和第二侧壁或第二器件隔离层的第一和第二侧壁的垂直延伸部对准的第一和第二侧壁。 此外，单元栅极图案的最下层和外围栅极图案的最下层包括不同的导电层。