公开(公告)号：US07160772B2

公开(公告)日：2007-01-09

申请号：US10906521

申请日：2005-02-23

Applicant: Douglas D. Coolbaugh ,  Vidhya Ramachandran

Inventor： Douglas D. Coolbaugh ,  Vidhya Ramachandran

IPC: H01L21/8242

CPC classification number: H01L23/5223 ,  H01L21/76808 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for integrating a metal-insulator-metal (MIM) capacitor in back end of line (BEOL) wiring levels of a semiconductor device includes forming an isolating layer over a lower wiring level, forming a bottom electrode of the capacitor on the isolating layer, and forming an interlevel dielectric material on the isolating layer and the bottom electrode. A capacitor dielectric is formed on the bottom electrode and a top electrode of the capacitor is formed on the capacitor dielectric, wherein the top electrode is formed concurrently with an upper wiring level, the upper level being the next successive wiring level with respect to the lower wiring level.

Abstract translation: 在半导体器件的后端（BEOL）布线层中集成金属 - 绝缘体 - 金属（MIM）电容器的方法包括在下布线层上形成隔离层，在隔离层上形成电容器的底电极 并且在隔离层和底部电极上形成层间电介质材料。 在底部电极上形成电容器电介质，并且在电容器电介质上形成电容器的顶部电极，其中顶部电极与上部布线电平同时形成，上部电平是相对于下部电极的下一个连续布线电平 接线等级。

公开(公告)号：US07135375B2

公开(公告)日：2006-11-14

申请号：US11053721

申请日：2005-02-08

Applicant: Douglas D. Coolbaugh ,  James S. Dunn ,  Michael D. Gordon ,  Mohamed Y. Hammad ,  Jeffrey B. Johnson ,  David C. Sheridan

Inventor： Douglas D. Coolbaugh ,  James S. Dunn ,  Michael D. Gordon ,  Mohamed Y. Hammad ,  Jeffrey B. Johnson ,  David C. Sheridan

IPC: H01L21/20 ,  H01L21/8222

CPC classification number: H01L27/0811 ,  H01L27/0808 ,  H01L29/93 ,  H01L29/94

Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.

公开(公告)号：US07098521B2

公开(公告)日：2006-08-29

申请号：US10711744

申请日：2004-10-01

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Alvin J. Joseph ,  Robert M. Rassel

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Alvin J. Joseph ,  Robert M. Rassel

IPC: H01L29/812

CPC classification number: H01L29/66143 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/872

Abstract: Schottky barrier diodes use a dielectric separation region to bound an active region. The dielectric separation region permits the elimination of a guard ring in at least one dimension. Further, using a dielectric separation region in an active portion of the integrated circuit device may reduce or eliminate parasitic capacitance by eliminating this guard ring.

Abstract translation: 肖特基势垒二极管使用介电分离区域结合活性区域。 电介质分离区允许在至少一个维度上消除保护环。 此外，在集成电路器件的有源部分中使用介质分离区可以通过消除该保护环来减少或消除寄生电容。

公开(公告)号：US06977398B2

公开(公告)日：2005-12-20

申请号：US10819732

申请日：2004-04-07

Applicant: Douglas D. Coolbaugh ,  Kathryn T. Schonenberg

Inventor： Douglas D. Coolbaugh ,  Kathryn T. Schonenberg

IPC: H01L21/265 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/10 ,  H01L29/737 ,  H01L31/0328

CPC classification number: H01L29/7378 ,  H01L21/26506 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/66242 ,  H01L29/66318

Abstract: A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

Abstract translation: 提供了一种改善SiGe双极性产率以及制造SiGe异质结双极晶体管的方法。 本发明的方法包括将碳C离子注入到器件的以下区域之一：集电极区域，子集电极区域，非本征基极区域和集电极 - 基极结区域。 在优选实施例中，上述每个区域包括C植入物。

公开(公告)号：US06939771B2

公开(公告)日：2005-09-06

申请号：US10653925

申请日：2003-09-04

Applicant: Arne W. Ballantine ,  Douglas D. Coolbaugh ,  Jeffrey Gilbert ,  Joseph R. Greco ,  Glenn R. Miller

Inventor： Arne W. Ballantine ,  Douglas D. Coolbaugh ,  Jeffrey Gilbert ,  Joseph R. Greco ,  Glenn R. Miller

IPC: H01L29/73 ,  H01L21/314 ,  H01L21/318 ,  H01L21/328 ,  H01L21/331 ,  H01L29/08

CPC classification number: H01L29/66272 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/0804 ,  H01L29/0895

Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

Abstract translation: 一种在半导体材料的两个区域之间形成至少一个界面区域的方法。 在半导体材料的两个区域的至少一部分边界附近形成包含氮的介电材料的至少一个区域，从而控制界面处的电阻。

公开(公告)号：US06876028B1

公开(公告)日：2005-04-05

申请号：US10605444

申请日：2003-09-30

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

IPC: H01L21/02 ,  H01L21/768 ,  H10L27/108 ,  H10L29/76 ,  H10L29/94 ,  H10L31/119

CPC classification number: H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

公开(公告)号：US06833299B2

公开(公告)日：2004-12-21

申请号：US10292204

申请日：2002-11-12

Applicant: Douglas D. Coolbaugh ,  James Stuart Dunn ,  Stephen Arthur St. Onge

Inventor： Douglas D. Coolbaugh ,  James Stuart Dunn ,  Stephen Arthur St. Onge

IPC: H01L218244

CPC classification number: H01L28/40 ,  H01L29/94

Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

Abstract translation: 一种用作BiCMOS器件中的组件的堆叠多晶硅/ MOS电容器，包括在其表面形成有具有第一导电类型的区域的半导体衬底; 形成在覆盖所述第一导电型区域的所述半导体衬底上的栅极氧化物; 形成在至少所述栅极氧化物层上的第一多晶硅层，所述第一多晶硅层掺杂有N或P型掺杂剂; 形成在所述第一多晶硅层上的电介质层; 以及形成在所述介电层上的第二多晶硅层，所述第二多晶硅层掺杂有与所述第一多晶硅层相同或不同的掺杂剂。

公开(公告)号：US06703283B1

公开(公告)日：2004-03-09

申请号：US09244958

申请日：1999-02-04

Applicant: Arne W. Ballantine ,  Douglas D. Coolbaugh ,  Jeffrey Gilbert ,  Joseph R. Greco ,  Glenn R. Miller

Inventor： Arne W. Ballantine ,  Douglas D. Coolbaugh ,  Jeffrey Gilbert ,  Joseph R. Greco ,  Glenn R. Miller

IPC: H01L21331

CPC classification number: H01L29/66272 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/0804 ,  H01L29/0895

Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

Abstract translation: 一种在半导体材料的两个区域之间形成至少一个界面区域的方法。 在半导体材料的两个区域的至少一部分边界附近形成包含氮的介电材料的至少一个区域，从而控制界面处的电阻。

公开(公告)号：US06528821B2

公开(公告)日：2003-03-04

申请号：US10093932

申请日：2002-03-08

Applicant: Douglas D. Coolbaugh ,  David L. Harame

Inventor： Douglas D. Coolbaugh ,  David L. Harame

IPC: H01L2976

CPC classification number: H01L21/26513 ,  H01L21/02381 ,  H01L21/02667 ,  H01L21/2022

Abstract: A method of forming a diffusion region in a silicon substrate having low-resistance, acceptable defect density, reliability and process control comprising the steps of: (a) subjecting a silicon substrate to a first ion implantation step, said first ion implantation step being conducted under conditions such that a region of amorphized Si is formed in said silicon substrate; (b) subjecting said silicon substrate containing said region of amorphized Si to a second ion implantation step, said second ion implantation step being carried out by implanting a dopant ion into said silicon substrate under conditions such that the peak of implant of said dopant ion is within the region of amorphized Si; and (c) annealing said silicon substrate under conditions such that said region of amorphized Si is re-crystallized thereby forming a diffusion region in said silicon substrate is provided.

公开(公告)号：US06507063B2

公开(公告)日：2003-01-14

申请号：US09551168

申请日：2000-04-17

Applicant: Douglas D. Coolbaugh ,  James Stuart Dunn ,  Stephen Arthur St. Onge

Inventor： Douglas D. Coolbaugh ,  James Stuart Dunn ,  Stephen Arthur St. Onge

IPC: H01L27108

CPC classification number: H01L28/40 ,  H01L29/94

Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

Abstract translation: 一种用作BiCMOS器件中的组件的堆叠多晶硅/ MOS电容器，包括在其表面形成有具有第一导电类型的区域的半导体衬底; 形成在覆盖所述第一导电型区域的所述半导体衬底上的栅极氧化物; 形成在至少所述栅极氧化物层上的第一多晶硅层，所述第一多晶硅层掺杂有N或P型掺杂剂; 形成在所述第一多晶硅层上的电介质层; 以及形成在所述介电层上的第二多晶硅层，所述第二多晶硅层掺杂有与所述第一多晶硅层相同或不同的掺杂剂。