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    Disaggregated computing for distributed confidential computing environment
    82.
    发明授权
    Disaggregated computing for distributed confidential computing environment 有权

    公开(公告)号：US12229605B2

    公开(公告)日：2025-02-18

    申请号：US18538171

    申请日：2023-12-13

    Applicant: Intel Corporation

    Inventor： Reshma Lal ,  Pradeep Pappachan ,  Luis Kida ,  Soham Jayesh Desai ,  Sujoy Sen ,  Selvakumar Panneer ,  Robert Sharp

    IPC: G06F9/50 ,  G06F9/38 ,  G06T1/20 ,  G06T1/60

    Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.

    Mechanism to update attested firmware on a platform
    83.
    发明授权
    Mechanism to update attested firmware on a platform 有权

    公开(公告)号：US12229270B2

    公开(公告)日：2025-02-18

    申请号：US18538787

    申请日：2023-12-13

    Applicant: Intel Corporation

    Inventor： Prashant Dewan ,  Nivedita Aggarwal

    IPC: G06F21/57 ,  H04L9/08

    Abstract: An apparatus to facilitate permissions at a computing system platform is disclosed. The apparatus includes a plurality of agents, each including a non-volatile memory storing firmware executed to perform a function associated with the agent and attestation hardware to detect an update at the computing system platform, generate a cryptographic key associated with each of the plurality of agents, perform an attestation with a relying party using the generated cryptographic keys and receive a tuple associated with each of the plurality of agents, wherein a tuple includes one or more permissions indicating platform resources an agent is permitted to access.

    Machine learning fraud resiliency using perceptual descriptors
    84.
    发明授权
    Machine learning fraud resiliency using perceptual descriptors 有权

    公开(公告)号：US12229254B2

    公开(公告)日：2025-02-18

    申请号：US17560943

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Raizy Kellermann ,  Omer Ben-Shalom ,  Alex Nayshtut

    IPC: G06F21/55 ,  G06V10/774 ,  G06V10/82 ,  G06V20/56

    Abstract: Machine learning fraud resiliency using perceptual descriptors is described. An example of a computer-readable storage medium includes instructions for accessing multiple examples in a training dataset for a classifier system; calculating one or more perceptual hashes for each of the examples; generating clusters of perceptual hashes for the multiple examples based on the calculation of the one or more perceptual hashes for each of the plurality of examples; obtaining an inference sample for classification by the classifier system; generating a first classification result for the inference sample utilizing a neural network classifier and generating a second classification result utilizing the generated clusters of perceptual hashes; comparing the first classification result with the second classification result; and, upon a determination that the first classification result does not match the second classification result, determining a suspicion of an adversarial attack.

    MULTI-CARRIER/BEAM LBT PROCEDURE ABOVE 52.6GHZ
    85.
    发明申请
    MULTI-CARRIER/BEAM LBT PROCEDURE ABOVE 52.6GHZ 有权

    公开(公告)号：US20250056598A1

    公开(公告)日：2025-02-13

    申请号：US18723547

    申请日：2023-02-09

    Applicant: Intel Corporation

    Inventor： Salvatore Talarico ,  Yi Wang ,  Yingyang Li ,  Gang Xiong ,  Dae Won LEE

    IPC: H04W74/00 ,  H04W74/0808

    Abstract: An apparatus and system of providing a listen before talk (LBT) procedure in multi-carrier or multi-beam mode above a 52.6 GHz band are described. The LBT procedure is performed independently for each carrier or beam to maintain and update a different back-off counter for each carrier or beam. To align a transmission starting time across the carriers or beams, for each carrier or beam: the counter continues to decrement if the counter has reached zero before the starting time and transmit at the starting time if the channel continues to be sensed idle for an additional observation period immediately prior to the starting time and otherwise considers the LBT procedure to have failed. The counter is reinitialized for carriers or beams for which a channel occupancy time (COT) is to be acquired and transmission ceases.

    Self-aligned gate endcap (SAGE) architectures with gate-all-around devices
    87.
    发明授权
    Self-aligned gate endcap (SAGE) architectures with gate-all-around devices 有权

    公开(公告)号：US12224350B2

    公开(公告)日：2025-02-11

    申请号：US18374959

    申请日：2023-09-29

    Applicant: Intel Corporation

    Inventor： Biswajeet Guha ,  William Hsu ,  Leonard P. Guler ,  Dax M. Crum ,  Tahir Ghani

    IPC: H01L21/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78

    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

    Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate
    88.
    发明授权
    Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate 有权

    公开(公告)号：US12224264B2

    公开(公告)日：2025-02-11

    申请号：US18385167

    申请日：2023-10-30

    Applicant: Intel Corporation

    Inventor： Rahul Jain ,  Ji Yong Park ,  Kyu Oh Lee

    IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

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