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    Methods of forming hemisperical grained silicon on a template on a semiconductor work object
    83.
    发明申请
    Methods of forming hemisperical grained silicon on a template on a semiconductor work object 审中-公开
    在半导体工件上的模板上形成半晶粒硅的方法

    公开(公告)号：US20050051082A1

    公开(公告)日：2005-03-10

    申请号：US10943612

    申请日：2004-09-17

    Applicant: Guoqing Chen ,  James Pan

    Inventor： Guoqing Chen ,  James Pan

    IPC: H01L21/02 ,  C30B23/00 ,  C30B1/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

    CPC classification number: H01L28/84 ,  H01L28/90

    Abstract: The present invention provides a method of preparing a surface of a silicon wafer for formation of HSG structures. The method contemplates providing a wafer having at least one HSG template comprising polysilicon formed in BPSG, the HSG template being covered by silicon dioxide. The wafer is treated with a cleaning agent to clean the surface of the wafer. Next, the wafer is treated with a conditioning agent. The conditioning agent removes native oxide from the HSG template without excessively etching structural BPSG. Preferably, the conditioning agent also removes a thin layer of polysilicon on the HSG template. The wafer is then transferred to a process chamber for HSG formation.

    Abstract translation: 本发明提供一种制备用于形成HSG结构的硅晶片的表面的方法。 该方法考虑提供具有包含在BPSG中形成的多晶硅的至少一个HSG模板的晶片，HSG模板被二氧化硅覆盖。 用清洁剂处理晶片以清洁晶片的表面。 接下来，用调理剂处理晶片。 调理剂从HSG模板中除去天然氧化物，而不会过度蚀刻结构BPSG。 优选地，调理剂还在HSG模板上除去薄层的多晶硅。 然后将晶片转移到用于HSG形成的处理室。

    Methods of forming hemispherical grained silicon on a template on a semiconductor work object
    84.
    发明授权
    Methods of forming hemispherical grained silicon on a template on a semiconductor work object 失效
    在半导体工件上的模板上形成半球形晶粒硅的方法

    公开(公告)号：US06835617B2

    公开(公告)日：2004-12-28

    申请号：US10361107

    申请日：2003-02-07

    Applicant: Guoqing Chen ,  James Pan

    Inventor： Guoqing Chen ,  James Pan

    IPC: H01L218242

    CPC classification number: H01L28/84 ,  H01L28/90

    Abstract: The present invention provides a method of preparing a surface of a silicon wafer for formation of HSG structures. The method contemplates providing a wafer having at least one HSG template comprising polysilicon formed in BPSG, the HSG template being covered by silicon dioxide. The wafer is treated with a cleaning agent to clean the surface of the wafer. Next, the wafer is treated with a conditioning agent. The conditioning agent removes native oxide from the HSG template without excessively etching structural BPSG. Preferably, the conditioning agent also removes a thin layer of polysilicon on the HSG template. The wafer is then transferred to a process chamber for HSG formation.

    Abstract translation: 本发明提供一种制备用于形成HSG结构的硅晶片的表面的方法。 该方法考虑提供具有包含在BPSG中形成的多晶硅的至少一个HSG模板的晶片，HSG模板被二氧化硅覆盖。 用清洁剂处理晶片以清洁晶片的表面。 接下来，用调理剂处理晶片。 调理剂从HSG模板中除去天然氧化物，而不会过度蚀刻结构BPSG。 优选地，调理剂还在HSG模板上除去薄层的多晶硅。 然后将晶片转移到用于HSG形成的处理室。

    High selectivity etching process for oxides
    85.
    发明授权
    High selectivity etching process for oxides 失效
    氧化物的高选择性蚀刻工艺

    公开(公告)号：US06355182B2

    公开(公告)日：2002-03-12

    申请号：US09780166

    申请日：2001-02-09

    Applicant: Randhir Thakur ,  James Pan

    Inventor： Randhir Thakur ,  James Pan

    IPC: D44C122

    CPC classification number: H01L28/40 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116

    Abstract: A process for etching oxides having differing densities which is not only highly selective, but which also produces uniform etches is provided and includes the steps of providing an oxide layer on a surface of a substrate, exposing the oxide layer to a liquid comprising a halide-containing species, and exposing the oxide layer to a gas phase comprising a halide-containing species. The process desirably is used to selectively etch a substrate surface in which the surface of the substrate includes on a first portion thereof a first silicon oxide and on a second portion thereof a second silicon oxide, with the first silicon oxide being relatively more dense than the second silicon oxide, such as, for example, a process which forms a capacitor storage cell on a semiconductor substrate.

    Abstract translation: 提供了不仅具有高选择性但也产生均匀蚀刻的具有不同密度的氧化物的方法，包括以下步骤：在衬底的表面上提供氧化物层，将氧化物层暴露于包含卤化物 - 并将氧化物层暴露于含有卤化物的物质的气相中。 该方法理想地用于选择性地蚀刻其中衬底的表面在其第一部分上包含第一氧化硅的衬底表面，并且在其第二部分上选择性地蚀刻第二氧化硅，其中第一氧化硅相对于 第二氧化硅，例如在半导体衬底上形成电容器存储单元的工艺。

    Ultra High Speed Navigation Magnetic Satellite and Unmanned Aircraft
    86.
    发明申请
    Ultra High Speed Navigation Magnetic Satellite and Unmanned Aircraft 审中-公开
    超高速导航磁卫星和无人机

    公开(公告)号：US20160004250A1

    公开(公告)日：2016-01-07

    申请号：US14322957

    申请日：2014-07-03

    Applicant: James Pan

    Inventor： James Pan

    IPC: G05D1/00 ,  B64C39/02 ,  B64C17/00 ,  B64G1/10

    CPC classification number: B64G1/10 ,  B64G1/244 ,  B64G1/32 ,  B64G1/409

    Abstract: The present invention is about a new satellite or unmanned aircraft guided by earth's magnetic fields, instead of gravitational fields, as in the case of traditional satellites. This type of magnetic satellites can fly many times faster than traditional satellites, and sustain a much heavier load if necessary. In order to navigate in earth's magnetic fields, the magnetic satellite needs to be heavily charged. The charges, interacting with the magnetic field, induce a magnetic force, which replaces the gravitational force as the centripetal force for circular motion.

    Abstract translation: 本发明涉及一种由地球磁场引导的新的卫星或无人驾驶飞机，而不是像传统卫星一样的重力场。 这种类型的磁卫星可以比传统卫星飞行多倍，如果需要，可以承受更重的载荷。 为了在地球磁场中导航，磁卫星需要充电。 与磁场相互作用的电荷引起磁力，其代替重力作为圆心运动的向心力。

    UCP4
    88.
    发明授权
    UCP4 有权

    公开(公告)号：US08313927B2

    公开(公告)日：2012-11-20

    申请号：US13236459

    申请日：2011-09-19

    Applicant: Sean Adams ,  James Pan ,  Alan Zhong

    Inventor： Sean Adams ,  James Pan ,  Alan Zhong

    IPC: C12P21/00 ,  C07K14/435 ,  C12N15/09

    CPC classification number: C07K14/4702 ,  A61K38/00 ,  A61K48/00 ,  C07K14/47 ,  C07K2319/00

    Abstract: The present invention is directed to a novel polypeptide, designated in the present application as “UCP4” (SEQ ID NO: 1), having homology to certain human uncoupling proteins (“UCPs”) and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention, and methods for producing the polypeptides of the present invention.

    Abstract translation: 本发明涉及本申请中命名为具有与某些人解偶联蛋白（UCP）和编码那些多肽的核酸分子具有同源性的UCP4（SEQ ID NO：1））的新型多肽。 本文还提供了包含那些核酸序列的载体和宿主细胞，包含与异源多肽序列融合的本发明多肽的嵌合多肽分子，与本发明的多肽结合的抗体，以及本发明多肽的制备方法 发明。

    STRUCTURE AND METHOD FOR FORMING SHIELDED GATE TRENCH FET WITH MULTIPLE CHANNELS
    89.
    发明申请
    STRUCTURE AND METHOD FOR FORMING SHIELDED GATE TRENCH FET WITH MULTIPLE CHANNELS 有权
    用于形成具有多个通道的屏蔽栅极晶体管的结构和方法

    公开(公告)号：US20120280312A1

    公开(公告)日：2012-11-08

    申请号：US13553285

    申请日：2012-07-19

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L29/78

    CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7831

    Abstract: In one embodiment, an apparatus can include a trench extending into a semiconductor region of a first conductivity type, an electrode disposed in the trench, and a source region of the first conductivity type abutting a sidewall of the trench. The apparatus can include a first well region of a second conductivity type disposed in the semiconductor region below the source region and abutting the sidewall of the trench lateral to the electrode where the second conductivity type is opposite the first conductivity type. The apparatus can also include a second well region of the second conductivity type disposed in the semiconductor region and abutting the sidewall of the trench, and a third well region of the first conductivity type disposed between the first well region and the second well region.

    Abstract translation: 在一个实施例中，装置可以包括延伸到第一导电类型的半导体区域中的沟槽，设置在沟槽中的电极以及与沟槽的侧壁邻接的第一导电类型的源极区域。 该装置可以包括设置在源极区域下方的半导体区域中的第二导电类型的第一阱区域，并且与第二导电类型与第一导电类型相反的电极的横向侧壁邻接沟槽的侧壁。 该装置还可以包括设置在半导体区域中并邻接沟槽的侧壁的第二导电类型的第二阱区域以及布置在第一阱区域和第二阱区域之间的第一导电类型的第三阱区域。

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