公开(公告)号：US07301210B2

公开(公告)日：2007-11-27

申请号：US11306827

申请日：2006-01-12

申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211

摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

摘要翻译： 公开了一种集成电路，其具有在相同基板上具有不同宽度和可变间隔的多个半导体散热片。 形成电路的方法包括使用不同类型的心轴的侧壁图像转印过程。 翅片厚度和翅片翅片间距由用于在心轴上形成氧化物侧壁的氧化工艺控制，更具体地，通过处理时间和使用固有的，氧化增强的和/或氧化抑制的心轴来控制。 翅片厚度也通过使用与氧化物侧壁结合或代替氧化物侧壁的侧壁间隔来控制。 具体地，单独的氧化物侧壁的图像，侧壁间隔物的图像和/或侧壁间隔物和氧化物侧壁的组合图像被转移到半导体层中以形成散热片。 可以使用具有不同厚度和可变间隔的散热片来形成单个多鳍FET，或者替代地，各种单鳍和/或多鳍FET。

公开(公告)号：US07298008B2

公开(公告)日：2007-11-20

申请号：US11275638

申请日：2006-01-20

申请人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

发明人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/7436 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203

摘要： Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

摘要翻译： 公开了一种硅控制整流器，制造硅控制整流器的方法和使用硅控整流器作为集成电路的静电放电保护器件。 硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为 在平行于水平面的单个水平方向上。

公开(公告)号：US07138313B2

公开(公告)日：2006-11-21

申请号：US10708912

申请日：2004-03-31

申请人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mujahid Muhammad ,  Christopher S. Putnam

发明人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mujahid Muhammad ,  Christopher S. Putnam

IPC分类号： H01L21/8234

CPC分类号： H01L27/0255 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66136 ,  H01L29/861

摘要： A method of forming a self-aligned SOI diode, the method comprising depositing a protective structure over a substrate; implanting a plurality of diffusion regions of variable dopant types in an area between at least one pair of isolation regions in the substrate, the plurality of diffusion regions separated by a diode junction, wherein the implanting aligns an upper surface of the diode junction with the protective structure; and removing the protective structure. The method further comprises forming a silicide layer over the diffusion regions and aligned with the protective structure. The protective structure comprises a hard mask, wherein the hard mask comprises a silicon nitride layer. Alternatively, the protective structure comprises a polysilicon gate and insulating spacers on opposite sides of the gate. Furthermore, in the removing step, the spacers remain on the substrate.

摘要翻译： 一种形成自对准SOI二极管的方法，所述方法包括在衬底上沉积保护结构; 在衬底中的至少一对隔离区域之间的区域中注入多个可变掺杂剂类型的扩散区域，所述多个扩散区域被二极管结点隔开，其中所述注入将所述二极管结的上表面与所述保护层 结构体; 并移除保护结构。 该方法还包括在扩散区上形成硅化物层并与保护结构对准。 保护结构包括硬掩模，其中硬掩模包括氮化硅层。 或者，保护结构包括在栅极的相对侧上的多晶硅栅极和绝缘间隔物。 此外，在去除步骤中，衬垫保留在衬底上。

公开(公告)号：US06774017B2

公开(公告)日：2004-08-10

申请号：US10190405

申请日：2002-07-03

申请人： Jeffrey Scott Brown ,  Andres Bryant ,  Robert J. Gauthier, Jr. ,  Randy William Mann ,  Steven Howard Voldman

发明人： Jeffrey Scott Brown ,  Andres Bryant ,  Robert J. Gauthier, Jr. ,  Randy William Mann ,  Steven Howard Voldman

IPC分类号： H01L2120

CPC分类号： H01L27/1203 ,  H01L21/26533 ,  H01L21/76232 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76283

摘要： A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.

摘要翻译： 一种半导体结构及其相关制造方法，包括具有连续掩埋氧化物层并具有多个沟槽隔离结构的衬底。 掩埋氧化物层可以位于衬底内的多于一个深度处。 沟槽隔离结构的几何形状可随深度而变化。 沟槽隔离结构可以接触或不接触埋入的氧化物层。 两个沟槽隔离结构可以将衬底穿透到相同的深度或不同的深度。 沟槽隔离结构在衬底内的区域之间提供绝缘分离，并且分离的区域可以包含半导体器件。 半导体结构便于在公共晶片上提供数字和模拟器件。 双深埋入氧化物层有利于非对称半导体结构。

公开(公告)号：US06646305B2

公开(公告)日：2003-11-11

申请号：US09915061

申请日：2001-07-25

申请人： Fariborz Assaderaghi ,  Andres Bryant ,  Peter E. Cottrell ,  Robert J. Gauthier, Jr. ,  Randy W. Mann ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Fariborz Assaderaghi ,  Andres Bryant ,  Peter E. Cottrell ,  Robert J. Gauthier, Jr. ,  Randy W. Mann ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L2701

CPC分类号： H01L27/1203 ,  H01L27/1104

摘要： A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.

摘要翻译： 一种半导体存储器件，包括：在衬底绝缘体的顶部上具有薄硅层的SOI衬底; 以及包括四个NFET和位于薄硅层中的两个PFET的SRAM，每个NFET和PFET具有在源极区域和漏极区域之间的主体区域，其中两个NFET的主体电连接到地。 另外，两个PFET的主体电连接到VDD。

公开(公告)号：US06512296B1

公开(公告)日：2003-01-28

申请号：US09636325

申请日：2000-08-10

申请人： Robert J. Gauthier, Jr. ,  Randy W. Mann ,  Steven H. Voldman

发明人： Robert J. Gauthier, Jr. ,  Randy W. Mann ,  Steven H. Voldman

IPC分类号： H01L2348

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/456

摘要： A process for forming heterogeneous silicide structures on a semiconductor substrate (10) includes implanting molybdenum ions into selective areas of the semiconductor substrate (10) to form molybdenum regions (73, 74, 75, 76). Titanium is then deposited over the semiconductor substrate (10). The semiconductor substrate (10) is annealed at a temperature between approximately 600° C. and approximately 700° C. During the annealing process, the titanium deposited in areas outside the molybdenum regions (73, 74, 75, 76) interacts with silicon on the substrate to form titanium silicide in a high resistivity C49 crystal phase. The titanium deposited in areas within the molybdenum regions (73, 74, 75, 76) interacts with silicon to form titanium silicide in a low resistivity C54 crystal phase because the presence of molybdenum ions in silicon lowers the energy barrier for crystal phase transformation between the C49 phase and the C54 phase.

摘要翻译： 在半导体衬底（10）上形成异质硅化物结构的方法包括将钼离子注入到半导体衬底（10）的选择区域中以形成钼区（73,74,75,76）。 然后将钛沉积在半导体衬底（10）上。 半导体衬底（10）在大约600℃和大约700℃之间的温度下退火。在退火过程中，沉积在钼区域（73,74,75,76）之外的区域中的钛与硅 该基板在高电阻率C49晶相中形成硅化钛。 在钼区域（73,74,75,76）中的区域中沉积的钛与硅相互作用以在低电阻率C54晶体相中形成硅化钛，因为硅中的钼离子的存在降低了能量势垒以进行晶体相变 C49相和C54相。

公开(公告)号：US06404236B1

公开(公告)日：2002-06-11

申请号：US09811967

申请日：2001-03-19

申请人： Kerry Bernstein ,  Andres Bryant ,  Robert J. Gauthier, Jr. ,  Edward Joseph Nowak ,  Minh Ho Tong

发明人： Kerry Bernstein ,  Andres Bryant ,  Robert J. Gauthier, Jr. ,  Edward Joseph Nowak ,  Minh Ho Tong

IPC分类号： H03K19096

CPC分类号： H03K19/0963

摘要： A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, an isolation transistor, and multiple evaluate transistors. Connected to a power supply, the precharge transistor receives a clock input. The isolation transistor is connected to ground and also receives the clock input. Each of the input transistors, which are coupled between the precharge transistor and the isolation transistor, receives a signal input. The gate dielectric thickness of the evaluate transistors is less than the gate dielectric thickness of the precharge transistor.

摘要翻译： 公开了具有时钟预充电的多米诺骨牌逻辑电路。 多米诺骨牌逻辑电路包括预充电晶体管，隔离晶体管和多个评估晶体管。 连接到电源，预充电晶体管接收时钟输入。 隔离晶体管连接到地，并接收时钟输入。 耦合在预充电晶体管和隔离晶体管之间的每个输入晶体管接收信号输入。 评估晶体管的栅介质厚度小于预充电晶体管的栅介质厚度。

公开(公告)号：US06288426B1

公开(公告)日：2001-09-11

申请号：US09514106

申请日：2000-02-28

申请人： Robert J. Gauthier, Jr. ,  Dominic J. Schepis ,  William R. Tonti ,  Steven H. Voldman

发明人： Robert J. Gauthier, Jr. ,  Dominic J. Schepis ,  William R. Tonti ,  Steven H. Voldman

IPC分类号： H01L2900

CPC分类号： H01L29/78648 ,  H01L21/76264 ,  H01L21/76286 ,  H01L21/763 ,  H01L23/3677 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Silicon is formed at selected locations on a substrate during fabrication of selected electronic components. A dielectric separation region is formed within the top silicon layer, and filled with a thermally conductive material. A liner material may be optionally deposited prior to depositing the thermally conductive material. In a second embodiment, a horizontal layer of thermally conductive material is also deposited in an oxide layer or bulk silicon layer below the top layer of silicon.

摘要翻译： 在选择的电子部件的制造期间，在基板上的选定位置处形成硅。 介电分离区形成在顶层硅层内，并填充有导热材料。 衬里材料可以在沉积导热材料之前任选地沉积。 在第二实施例中，水平导热材料层也沉积在硅顶层之下的氧化物层或体硅层中。

公开(公告)号：US06232163B1

公开(公告)日：2001-05-15

申请号：US09362549

申请日：1999-07-28

申请人： Steven H. Voldman ,  Robert J. Gauthier, Jr. ,  Jeffrey S. Brown

发明人： Steven H. Voldman ,  Robert J. Gauthier, Jr. ,  Jeffrey S. Brown

IPC分类号： H01L218238

CPC分类号： H01L27/0811 ,  H01L29/7391 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high voltage tolerant diode structure for mixed-voltage, and mixed signal and analog/digital applications. The preferred silicon diode includes a polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. A well or an implanted area is formed in a bulk semiconductor substrate or in a surface silicon layer on an SOI wafer. Voltage applied to the polysilicon gate film, electrically depletes it, reducing voltage stress across the dielectric film. An intrinsic polysilicon film may be counter-doped, implanted with a low doped implantation, implanted with a low doped source/drain implant, or with a low doped MOSFET LDD or extension implant. Alternatively, a block mask may be formed over the gate structure when defining the depleted-polysilicon gate silicon diode to form low series resistance diode implants, preventing over-doping the film. Optionally, a hybrid photoresist method may be used to form higher doped edge implants in the silicon to reduce diode series resistance without a block mask.

摘要翻译： 用于混合电压，混合信号和模拟/数字应用的高耐压二极管结构。 优选的硅二极管包括在半导体（硅）层或主体上的至少一个电介质膜层上的多晶硅栅极结构。 阱体或植入区域形成在SOI半导体衬底或SOI晶片的表面硅层中。 施加到多晶硅栅极膜的电压，电耗电，降低电介质膜两端的电压。 本征多晶硅膜可以是反掺杂的，注入低掺杂注入，注入低掺杂源/漏注入，或者与低掺杂的MOSFET LDD或延伸注入。 或者，当限定耗尽多晶硅栅极硅二极管以形成低串联电阻二极管植入物时，可以在栅极结构上形成块掩模，防止膜过度掺杂。 可选地，可以使用混合光致抗蚀剂方法在硅中形成更高掺杂的边缘注入，以减少二极管串联电阻而不使用块掩模。

公开(公告)号：US6034388A

公开(公告)日：2000-03-07

申请号：US79846

申请日：1998-05-15

申请人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

IPC分类号： H01L21/334 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/12 ,  H01L29/94 ,  H01L29/76

CPC分类号： H01L29/66181 ,  H01L21/76237 ,  H01L21/76264 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/94 ,  H01L21/76283 ,  Y10S257/907

摘要： A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device. A polycrystalline silicon edge spacer is formed on each side of the gate conductor. A first pair of first conductivity type impurity diffusion regions are formed adjacent to the polycrystalline silicon edge spacers. The polycrystalline silicon film and edge spacers lie on a portion of the substrate between the first pair of first conductivity type impurity diffusion regions. The first pair of first conductivity type impurity diffusion regions have an impurity concentration substantially lower than the standard impurity concentration for the gate conductor of an MOS device. The gate conductor and the first pair of first conductivity type impurity diffusion regions may be formed by a single implantation step. Applications include ESD protection, analog applications, peripheral input/output circuitry, decoupling capacitors, and resistor ballasting.

摘要翻译： 一种包括半导体衬底的电路元件。 第一导电类型的阱区形成在衬底的表面中。 在基板上形成电介质膜。 在衬底的阱区上的电介质膜上形成第一导电类型的栅极导体。 栅极导体由多晶硅膜形成。 栅极导体的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。 在栅极导体的每一侧上形成多晶硅边缘隔离物。 第一对第一导电型杂质扩散区形成在与多晶硅边缘隔离物相邻的位置。 多晶硅膜和边缘隔离物位于第一对第一导电型杂质扩散区之间的衬底的一部分上。 第一对第一导电型杂质扩散区的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。 可以通过单个注入步骤形成栅极导体和第一对第一导电型杂质扩散区。 应用包括ESD保护，模拟应用，外围输入/输出电路，去耦电容和电阻镇流器。