公开(公告)号：US06574700B2

公开(公告)日：2003-06-03

申请号：US09986347

申请日：2001-11-08

申请人： Seiji Miura ,  Kazushige Ayukawa

发明人： Seiji Miura ,  Kazushige Ayukawa

IPC分类号： G06F1200

CPC分类号： G06F13/161 ,  G06F12/0215 ,  G11C7/1018 ,  Y02D10/13 ,  Y02D10/14

摘要： A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

摘要翻译： 存储器控制器和数据处理器响应于连续访问不同页面的事件，将其操作模式从用于高速访问的页面模式切换到同一页面到页面关闭模式，从而执行存储器访问 在高速和低功耗下。

公开(公告)号：US06392950B2

公开(公告)日：2002-05-21

申请号：US09803958

申请日：2001-06-29

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

IPC分类号： G11C800

CPC分类号： G11C11/005 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/143 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/4076 ,  H01L2224/06145 ,  H01L2224/06156 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

摘要翻译： 为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。 控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。 在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。 它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。

公开(公告)号：US09176907B2

公开(公告)日：2015-11-03

申请号：US13058857

申请日：2009-08-10

申请人： Seiji Miura

发明人： Seiji Miura

IPC分类号： G06F12/00 ,  G06F13/16

CPC分类号： G06F13/1689 ,  Y02D10/14

摘要： A high-speed, low-cost data processing system capable of ensuring expandability of memory capacity and having excellent usability while keeping constant latency is provided. The data processing system is configured to include a data processing device, a volatile memory, and a non-volatile memory. As the data processing device, the volatile memory, and the non-volatile memory are connected in series and the number of connection signals are reduced, the speed is increased while keeping expandability of memory capacity. The data processing device measures latency and performs a latency correcting operation to keep the latency constant. When data in the non-volatile memory is transferred to the volatile memory, error correction is performed to improve reliability. The data processing system formed of these plurality of chips is configured as a data processing system module in which the chips are disposed so as to be multilayered each other and are connected by a ball grid array (BGA) or a technology of wiring these chips.

摘要翻译： 提供了一种高速，低成本的数据处理系统，其能够确保存储容量的可扩展性并且具有优异的可用性，同时保持恒定的延迟。 数据处理系统被配置为包括数据处理设备，易失性存储器和非易失性存储器。 作为数据处理装置，易失性存储器和非易失性存储器被串联连接，并且连接信号的数量减少，在保持存储器容量的可扩展性的同时增加速度。 数据处理设备测量延迟并执行等待时间校正操作以保持等待时间恒定。 当非易失性存储器中的数据被传送到易失性存储器时，执行错误校正以提高可靠性。 由这些多个芯片形成的数据处理系统被配置为数据处理系统模块，其中芯片被布置为彼此多层并且通过球栅阵列（BGA）或这些芯片的布线技术连接。

公开(公告)号：US08904140B2

公开(公告)日：2014-12-02

申请号：US13321333

申请日：2009-05-22

申请人： Seiji Miura

发明人： Seiji Miura

IPC分类号： G06F13/00 ,  G11C7/00 ,  G06F13/16 ,  G11C7/22

CPC分类号： G06F3/0688 ,  G06F3/0619 ,  G06F3/0655 ,  G06F13/161 ,  G11C7/22

摘要： Provided is a user-friendly information processing system which is capable of maintaining latency within a fixed range and ensuring the expandability of a memory capacity at high speed and low cost. The information processing system, including an information processing device, a volatile memory, and nonvolatile memories, is configured. The information processing device, the volatile memory, and the nonvolatile memories are connected in series with one another to reduce the number of connection signals, thereby realizing speeding-up while maintaining the expandability of the memory capacity. The information processing device manages response time zones and time zones where responses overlap one another, and performs a correction operation on the latency, thereby realizing fast data transfer while maintaining the latency within the fixed range. The information processing device performs an error correction to improve the reliability when transferring the data of the nonvolatile memories to the volatile memory. The information processing system composed of a plurality of chips is configured as an information processing system/module in which the respective chips are arranged in layers, and wired together by a through via.

摘要翻译： 提供了一种用户友好的信息处理系统，其能够将等待时间保持在固定范围内，并且以高速和低成本确保存储器容量的可扩展性。 构成包括信息处理装置，易失性存储器和非易失性存储器的信息处理系统。 信息处理装置，易失性存储器和非易失性存储器彼此串联连接以减少连接信号的数量，从而在保持存储容量的可扩展性的同时实现加速。 信息处理装置管理响应重叠的响应时区和时区，对等待时间执行校正操作，从而实现快速数据传送，同时将等待时间保持在固定范围内。 信息处理装置执行错误校正，以在将非易失性存储器的数据传送到易失性存储器时提高可靠性。 由多个芯片组成的信息处理系统被配置为信息处理系统/模块，其中各个芯片被布置成层，并且通过通孔连接在一起。

公开(公告)号：US08432716B2

公开(公告)日：2013-04-30

申请号：US12926706

申请日：2010-12-06

申请人： Seiji Miura ,  Kazushige Ayukawa

发明人： Seiji Miura ,  Kazushige Ayukawa

IPC分类号： G11C5/05

CPC分类号： G06F12/0246 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/005 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40607 ,  G11C11/412 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C29/70

摘要： A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

公开(公告)号：US08429355B2

公开(公告)日：2013-04-23

申请号：US12962753

申请日：2010-12-08

申请人： Seiji Miura

发明人： Seiji Miura

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F5/12 ,  G06F13/1663 ,  G06F13/1673

摘要： In an information processor system including a memory device (MEM0), a memory control device (SL0) capable of controlling an operation of the memory device, and a plurality of bus masters (MS0 to MS3) capable of giving access to the memory device through the memory control device, the memory control device includes a control circuit (SDCON) capable of giving a notice of information about a time that a data transfer from the memory device can be started to the bus master related to an access request. The bus master can cause the time information thus given to be a judgment factor as to whether an access request is given to the memory device or not. Consequently, each of the bus masters can avoid the generation of a useless access request and a data transfer to the masters to be accessed can be carried out smoothly.

公开(公告)号：US20120265925A1

公开(公告)日：2012-10-18

申请号：US13443883

申请日：2012-04-10

申请人： Seiji MIURA

发明人： Seiji MIURA

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7209 ,  G06F2212/7211 ,  G11C13/0004

摘要： A control circuit of a semiconductor device (memory module) realizes long life and others by a mechanism that suppresses and smoothes variations in use of a memory by equalizing the sizes of data write and data erase with respect to a data write request and sequentially allocating and using addresses of the memory in data write to an overwritable non-volatile memory device without carrying out an overwriting operation even in the case of an overwrite request. The control circuit realizes data write by a set of two types of operations of (a) an operation of erasing data of a first address or an operation of setting a flag value to an invalid state and (b) an operation of writing data to a second address different from the first address or an operation of setting a flag value to a valid state.

摘要翻译： 半导体器件（存储器模块）的控制电路通过均衡相对于数据写入请求的数据写入和数据擦除的大小来抑制和平滑存储器的使用变化的机制来实现长寿命等， 即使在重写请求的情况下，也可以使用写入可重写非易失性存储器件的数据中的存储器的地址，而不执行重写操作。 控制电路通过以下两种操作来实现数据写入：（a）擦除第一地址的数据或将标志值设置为无效状态的操作，以及（b）将数据写入到 第二地址不同于第一地址或将标志值设置为有效状态的操作。

公开(公告)号：US20120066432A1

公开(公告)日：2012-03-15

申请号：US13321333

申请日：2009-05-22

申请人： Seiji Miura

发明人： Seiji Miura

IPC分类号： G06F12/00

CPC分类号： G06F3/0688 ,  G06F3/0619 ,  G06F3/0655 ,  G06F13/161 ,  G11C7/22

摘要： Provided is a user-friendly information processing system which is capable of maintaining latency within a fixed range and ensuring the expandability of a memory capacity at high speed and low cost. The information processing system, including an information processing device, a volatile memory, and nonvolatile memories, is configured. The information processing device, the volatile memory, and the nonvolatile memories are connected in series with one another to reduce the number of connection signals, thereby realizing speeding-up while maintaining the expandability of the memory capacity. The information processing device manages response time zones and time zones where responses overlap one another, and performs a correction operation on the latency, thereby realizing fast data transfer while maintaining the latency within the fixed range. The information processing device performs an error correction to improve the reliability when transferring the data of the nonvolatile memories to the volatile memory. The information processing system composed of a plurality of chips is configured as an information processing system/module in which the respective chips are arranged in layers, and wired together by a through via.

摘要翻译： 提供了一种用户友好的信息处理系统，其能够将等待时间保持在固定范围内，并且以高速和低成本确保存储器容量的可扩展性。 构成包括信息处理装置，易失性存储器和非易失性存储器的信息处理系统。 信息处理装置，易失性存储器和非易失性存储器彼此串联连接以减少连接信号的数量，从而在保持存储容量的可扩展性的同时实现加速。 信息处理装置管理响应重叠的响应时区和时区，对等待时间执行校正操作，从而实现快速数据传送，同时将等待时间保持在固定范围内。 信息处理装置执行错误校正，以在将非易失性存储器的数据传送到易失性存储器时提高可靠性。 由多个芯片组成的信息处理系统被配置为信息处理系统/模块，其中各个芯片被布置成层，并且通过通孔连接在一起。

公开(公告)号：US20110145500A1

公开(公告)日：2011-06-16

申请号：US13058857

申请日：2009-08-10

申请人： Seiji Miura

发明人： Seiji Miura

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F13/1689 ,  Y02D10/14

摘要： A high-speed, low-cost data processing system capable of ensuring expandability of memory capacity and having excellent usability while keeping constant latency is provided. The data processing system is configured to include a data processing device, a volatile memory, and a non-volatile memory. As the data processing device, the volatile memory, and the non-volatile memory are connected in series and the number of connection signals are reduced, the speed is increased while keeping expandability of memory capacity. The data processing device measures latency and performs a latency correcting operation to keep the latency constant. When data in the non-volatile memory is transferred to the volatile memory, error correction is performed to improve reliability. The data processing system formed of these plurality of chips is configured as a data processing system module in which the chips are disposed so as to be multilayered each other and are connected by a ball grid array (BGA) or a technology of wiring these chips.

摘要翻译： 提供了一种高速，低成本的数据处理系统，其能够确保存储容量的可扩展性并且具有优异的可用性，同时保持恒定的延迟。 数据处理系统被配置为包括数据处理设备，易失性存储器和非易失性存储器。 作为数据处理装置，易失性存储器和非易失性存储器被串联连接，并且连接信号的数量减少，在保持存储器容量的可扩展性的同时增加速度。 数据处理设备测量延迟并执行等待时间校正操作以保持等待时间恒定。 当非易失性存储器中的数据被传送到易失性存储器时，执行错误校正以提高可靠性。 由这些多个芯片形成的数据处理系统被配置为数据处理系统模块，其中芯片被布置为彼此多层并且通过球栅阵列（BGA）或这些芯片的布线技术连接。

公开(公告)号：US20110078366A1

公开(公告)日：2011-03-31

申请号：US12926706

申请日：2010-12-06

申请人： Seiji Miura ,  Kazushige Ayukawa

发明人： Seiji Miura ,  Kazushige Ayukawa

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0246 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/005 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40607 ,  G11C11/412 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C29/70

摘要： A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

摘要翻译： 一种包括大容量非易失性存储器和至少一个随机存取存储器的半导体器件，所述设备的访问时间与每个随机存取存储器的访问时间相匹配。 半导体存储器件包括：具有第一读取时间的非易失性存储器FLASH; 具有比第一读取时间短100倍的第二读取时间的随机存取存储器DRAM; 电路，其包括连接到FLASH和DRAM两者的控制电路，并且能够控制对那些FLASH和DRAM的访问; 以及连接到电路的多个I / O端子。 结果，在访问DRAM之前，将FLASH数据传送到DRAM，从而与FLASH和DRAM之间的访问时间相匹配。 数据根据需要从DRAM写回到FLASH，从而保持FLASH和DRAM之间的数据匹配并存储数据。