公开(公告)号：US20240282371A1

公开(公告)日：2024-08-22

申请号：US18180864

申请日：2023-03-09

Applicant: United Microelectronics Corp.

Inventor： Yi Ting Hung ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: G11C13/00

CPC classification number: G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0045

Abstract: A forming operation method of a resistive random access memory is provided. The method includes the following steps. A positive pulse and a negative pulse are sequentially applied, by a bit line/source line driver, to multiple resistive random access memory cells in a direction form a farthest location to a nearest location based on the bit line/source line driver through a bit line and a source line to break down a dielectric film of each of the resistive random access memory cells and generate a conductive filament of each of the resistive random access memory cells.

公开(公告)号：US12069955B2

公开(公告)日：2024-08-20

申请号：US17363023

申请日：2021-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Po-Kai Hsu ,  Jing-Yin Jhang

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a first magnetic tunneling junction (MTJ) on a substrate, forming a first top electrode on the first MTJ, and then forming a passivation layer around the first MTJ. Preferably, the passivation layer includes a V-shape and a valley point of the V-shape is higher than a top surface of the first top electrode.

公开(公告)号：US20240268124A1

公开(公告)日：2024-08-08

申请号：US18636306

申请日：2024-04-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Chien-Ting Lin

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  G11C11/161 ,  H10B61/10 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

公开(公告)号：US20240266286A1

公开(公告)日：2024-08-08

申请号：US18118093

申请日：2023-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Wei Huang ,  Po-Hung Chen ,  Chun-Cheng Yu ,  I-Hsien Liu ,  Ho-Yu Lai ,  Kuan-Wen Fang ,  Chih-Sheng Chang

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76892

Abstract: A semiconductor pattern is provided in the present invention, including a first line extending to one end in a first direction and a second line extending in a second direction perpendicular to the first direction and adjacent to the end of the first line in the first direction, wherein the end of the first line is provided with a rounding feature, the first line has a width in the second direction, and the width is gradually increased to a maximum width toward the end and gradually converged to form the rounding feature.

公开(公告)号：US12058851B2

公开(公告)日：2024-08-06

申请号：US18199346

申请日：2023-05-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Hsu-Yang Wang ,  Chun-Chieh Chiu ,  Shih-Fang Tzou

IPC: H01L21/48 ,  H01L21/768 ,  H10B12/00

CPC classification number: H10B12/485 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76895 ,  H10B12/053 ,  H10B12/482

Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

公开(公告)号：US12057313B2

公开(公告)日：2024-08-06

申请号：US17556972

申请日：2021-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/8258 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/02565 ,  H01L21/8258 ,  H01L29/66969 ,  H01L29/7869

Abstract: The present invention provides a semiconductor structure, including a substrate, a thin-film transistor (TFT) on the substrate, wherein the thin-film transistor including a TFT channel layer, a first source and a first drain in the TFT channel layer and a first capping layer on the TFT channel layer. A MOSFET is on the substrate, with a second gate, a second source and a second drain on two sides of the second gate and a second capping layer on the second gate, wherein top surfaces of the second capping layer and the first capping layer are leveled, and a first ILD layer is on the first capping layer and the second capping layer, wherein the first ILD layer and the first capping layer function collectively as a gate dielectric layer for the TFT.

公开(公告)号：US20240260489A1

公开(公告)日：2024-08-01

申请号：US18635027

申请日：2024-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/8265 ,  H10N70/021 ,  H10N70/245 ,  H10N70/841 ,  H10N70/8833

Abstract: A semiconductor memory device includes a substrate, a first dielectric layer on the substrate, a bottom electrode on the first dielectric layer, a second dielectric layer on the first dielectric layer, and a top electrode in the second dielectric layer. The top electrode has a lower portion around the bottom electrode and a tapered upper portion. A third dielectric layer is disposed above the bottom electrode and around the tapered upper portion of the top electrode. A resistive-switching layer is disposed between a sidewall of the bottom electrode and a sidewall of the lower portion of the top electrode and between the third dielectric layer and a sidewall of the tapered upper portion of the top electrode. An air gap is disposed in the third dielectric layer.

公开(公告)号：US20240258378A1

公开(公告)日：2024-08-01

申请号：US18632253

申请日：2024-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Hua Chang ,  Jian-Feng Li ,  Hsiang-Chieh Yen

IPC: H01L29/15 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/157 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/30625 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, the semiconductor device including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.

公开(公告)号：US12052932B2

公开(公告)日：2024-07-30

申请号：US18132989

申请日：2023-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Rai-Min Huang ,  I-Fan Chang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01

Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape.

公开(公告)号：US12051740B2

公开(公告)日：2024-07-30

申请号：US17367640

申请日：2021-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Hsun-Wen Wang

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/0649 ,  H01L29/66462 ,  H01L29/6656

Abstract: A high electron mobility transistor includes an epitaxial stack on a substrate, a gate structure on the epitaxial stack, a passivation layer on the epitaxial stack and covering the gate structure, and an air gap between the passivation layer and the gate structure.