Method to make silicon nanoparticle from silicon rich-oxide by DC reactive sputtering for electroluminescence application
    81.
    发明申请
    Method to make silicon nanoparticle from silicon rich-oxide by DC reactive sputtering for electroluminescence application 审中-公开
    通过用于电致发光应用的DC反应溅射从富硅氧化物制造硅纳米颗粒的方法

    公开(公告)号:US20060172555A1

    公开(公告)日:2006-08-03

    申请号:US11049594

    申请日:2005-02-01

    CPC classification number: C23C14/5806 C23C14/10

    Abstract: A method of forming a silicon-rich silicon oxide layer having nanometer sized silicon particles therein includes preparing a substrate; preparing a target; placing the substrate and the target in a sputtering chamber; setting the sputtering chamber parameters; depositing material from the target onto the substrate to form a silicon-rich silicon oxide layer; and annealing the substrate to form nanometer sized silicon particles therein.

    Abstract translation: 形成其中具有纳米尺寸硅颗粒的富硅氧化硅层的方法包括制备衬底; 准备一个目标 将基板和靶放置在溅射室中; 设置溅射室参数; 将材料从靶材沉积到衬底上以形成富硅氧化硅层; 并对衬底退火以在其中形成纳米尺寸的硅颗粒。

    Method of making a non-volatile memory using a plasma oxidized high-k charge-trapping layer
    82.
    发明授权
    Method of making a non-volatile memory using a plasma oxidized high-k charge-trapping layer 失效
    使用等离子体氧化的高k电荷捕获层制造非易失性存储器的方法

    公开(公告)号:US06998317B2

    公开(公告)日:2006-02-14

    申请号:US10741802

    申请日:2003-12-18

    Applicant: Yoshi Ono

    Inventor: Yoshi Ono

    CPC classification number: H01L27/11568 H01L21/28282 H01L27/105 H01L27/11573

    Abstract: A method of fabricating a non-volatile memory device includes preparing a substrate; depositing a layer of HfO2 by atomic layer deposition; annealing the substrate and HfO2 layer in situ; exposing the HfO2 layer to a plasma discharge, thereby forming a charge-trapping layer; depositing a gate structure; and completing the memory device.

    Abstract translation: 一种制造非易失性存储器件的方法包括:制备衬底; 通过原子层沉积沉积一层HfO 2 O 2; 原位退火衬底和HfO 2层; 将HfO 2层暴露于等离子体放电,从而形成电荷捕获层; 沉积栅结构; 并完成存储设备。

    Electrode materials with improved hydrogen degradation resistance
    84.
    发明授权
    Electrode materials with improved hydrogen degradation resistance 失效
    具有改善耐氢降解性的电极材料

    公开(公告)号:US06833572B2

    公开(公告)日:2004-12-21

    申请号:US10229603

    申请日:2002-08-27

    CPC classification number: H01L28/75 H01L21/31604 H01L21/31683 H01L28/55

    Abstract: An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer; and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platinum and iridium, and a second metal taken from the group of metals consisting of aluminum and titanium; wherein the top electrode acts as a passivation layer and wherein the top electrode remains conductive following high temperature annealing in a hydrogen atmosphere. A method of forming a hydrogen-resistant electrode in a ferroelectric device includes forming a bottom electrode; forming a ferroelectric layer on the bottom electrode; depositing a top electrode on the ferroelectric layer; including depositing, simultaneously, a first metal taken from the group of metals consisting of platinum and iridium; and a second metal taken from the group of metals consisting of aluminum and titanium; and forming a passivation layer by annealing the structure in an oxygen atmosphere to form an oxide passivation layer on the top electrode.

    Abstract translation: 用于铁电体器件的电极包括底部电极; 铁电层 以及形成在强电介质层上并由金属组合形成的顶部电极,其包括从由铂和铱组成的金属组中的第一金属取得的金属和从由铝和钛组成的金属组中的第二金属; 其中所述顶部电极用作钝化层,并且其中所述顶部电极在氢气氛中的高温退火之后保持导电。 在铁电体器件中形成耐氢电极的方法包括形成底电极; 在底部电极上形成铁电层; 在铁电层上沉积顶部电极; 包括同时从由铂和铱组成的金属组中取出的第一金属; 和从由铝和钛组成的金属组中获取的第二金属; 以及通过在氧气氛中对所述结构退火以在所述顶部电极上形成氧化物钝化层来形成钝化层。

    Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate
    85.
    发明授权
    Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate 有权
    使用原子层沉积在基底上沉积高介电常数材料的方法

    公开(公告)号:US06420279B1

    公开(公告)日:2002-07-16

    申请号:US09894941

    申请日:2001-06-28

    CPC classification number: C23C16/45529 C23C16/405 H01L21/31604

    Abstract: Methods of forming hafnium oxide, zirconium oxide and nanolaminates of hafnium oxide and zirconium oxide are provided. These methods utilize atomic layer deposition techniques incorporating nitrate-based precursors, such as hafnium nitrate and zirconium nitrate. The use of these nitrate based precursors is well suited to forming high dielectric constant materials on hydrogen passivated silicon surfaces.

    Abstract translation: 提供了氧化铪和氧化锆形成氧化铪,氧化锆和Nanolaminates的方法。 这些方法利用纳入硝酸盐的前体,如硝酸铪和硝酸锆的原子层沉积技术。 使用这些基于硝酸盐的前体非常适合于在氢钝化硅表面上形成高介电常数材料。

    Method of forming ferroelastic lead germanate thin films
    86.
    发明授权
    Method of forming ferroelastic lead germanate thin films 有权
    形成铁弹性锗酸铅薄膜的方法

    公开(公告)号:US06410346B1

    公开(公告)日:2002-06-25

    申请号:US10010186

    申请日:2001-12-06

    Abstract: A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.

    Abstract translation: 提供Pb3GeO5相PGO薄膜。 该薄膜具有铁弹性,使其成为许多微机电应用或高速多芯片模块中的去耦电容器的理想选择。 该PGO膜在MOCVD工艺中唯一形成,其允许沉积小于1mm的薄膜。 该方法在溶剂中混合Pd和锗。 将溶液加热以形成分解的前体蒸汽。 该方法提供沉积温度和压力。 沉积的膜也被退火以增强膜的铁弹性特征。 还提供了由本发明PGO膜制成的铁弹性电容器。

    Method of forming nitrogen implanted ultrathin gate oxide for dual gate CMOS devices
    87.
    发明授权
    Method of forming nitrogen implanted ultrathin gate oxide for dual gate CMOS devices 失效
    用于双栅极CMOS器件形成氮化物超薄栅极氧化物的方法

    公开(公告)号:US06184110B2

    公开(公告)日:2001-02-06

    申请号:US09071234

    申请日:1998-04-30

    Inventor: Yoshi Ono Yanjun Ma

    CPC classification number: H01L21/28185 H01L21/28202 H01L29/511 H01L29/518

    Abstract: A method of forming a nitrogen-implanted gate oxide in a semiconductor device includes preparing a silicon substrate; forming an oxide layer on the prepared substrate; and implanting N+ or N2+ ions into the oxide layer in a plasma immersion ion implantation apparatus.

    Abstract translation: 在半导体器件中形成氮注入栅极氧化物的方法包括制备硅衬底; 在所制备的基板上形成氧化物层; 以及在等离子体浸没离子注入装置中将N +或N2 +离子注入到氧化物层中。

    Multilayered barrier metal thin-films
    88.
    发明授权
    Multilayered barrier metal thin-films 有权
    多层阻隔金属薄膜

    公开(公告)号:US08264081B2

    公开(公告)日:2012-09-11

    申请号:US11311546

    申请日:2005-12-19

    CPC classification number: H01L21/28562 H01L21/76841 H01L2221/1078

    Abstract: A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

    Abstract translation: 通过原子层化学气相沉积(ALCVD)将多层阻挡金属薄膜沉积在衬底上。 多层膜可以包括单个化学物质的几个不同层,或者各个不同的或交替的化学物质的几个层。 在优选实施例中,多层阻挡薄膜包括在衬底上的氮化钽层,其上沉积有氮化钛层。 整个多层膜的厚度可以是大约50埃。 当与通过常规化学气相沉积(CVD)沉积的膜相比时,该膜具有优异的膜特性,例如抗扩散能力,低电阻率,高密度和台阶覆盖。 本发明的多层阻挡金属薄膜具有改善的粘合特性,特别适用于其上的铜膜的金属化。

    Sub-resolutional grayscale reticle
    89.
    发明授权
    Sub-resolutional grayscale reticle 有权
    子分辨灰度光罩

    公开(公告)号:US07887980B2

    公开(公告)日:2011-02-15

    申请号:US12193568

    申请日:2008-08-18

    CPC classification number: G03F1/50 G03F7/0005

    Abstract: A sub-resolutional grayscale reticle and associated fabrication method have been presented. The method provides a transparent substrate, and forms a plurality of coincident partial-light transmissive layers overlying the transparent substrate. A pattern is formed, sub-resolutional at a first wavelength, in at least one of the transmissive layers. If there are n transmissive layers, the reticle transmits at least (n+1) intensities of light. In one aspect, each of the plurality of transmissive layers has the same extinction coefficient and the same thickness. In other aspects, the transmissive layers may have different thickness. Then, even if the extinction coefficients are the same, the attenuation of light through each layer is different. The transmission characteristics of the reticle can be further varied if the transmissive layers have different extinction coefficients. Likewise, the transmission characteristics through the sub-resolutional patterns can be varied.

    Abstract translation: 已经提出了一种亚分辨灰度标线和相关的制造方法。 该方法提供透明基板,并且形成覆盖透明基板的多个重合部分透光层。 在至少一个透射层中形成在第一波长处副溶液的图案。 如果存在n个透射层,则光罩传播至少(n + 1)个光强。 在一个方面,多个透射层中的每一个具有相同的消光系数和相同的厚度。 在其它方面,透射层可以具有不同的厚度。 那么即使消光系数相同,每层的光的衰减也是不同的。 如果透射层具有不同的消光系数,则可以进一步改变掩模版的透射特性。 同样,可以改变通过子解决图案的传输特性。

    Method of fabricating grayscale mask using smart cut® wafer bonding process
    90.
    发明授权
    Method of fabricating grayscale mask using smart cut® wafer bonding process 有权
    使用smartcut®晶圆接合工艺制造灰度掩模的方法

    公开(公告)号:US07838174B2

    公开(公告)日:2010-11-23

    申请号:US11657258

    申请日:2007-01-24

    CPC classification number: G03F1/50 H01L27/14685

    Abstract: A method of fabricating a grayscale mask includes preparing a silicon wafer; depositing a layer of Si3N4 directly on the silicon wafer; implanting H+ ions into the silicon wafer to form a defect layer; depositing a first layer of SiOxNy directly on the Si3N4 layer; depositing a layer of SRO directly on the first layer of SiOxNy; patterning and etching the SRO layer to form a microlens array in the SRO layer; depositing a second layer of SiOxNy on the SRO microlens array; CMP to planarize the second layer of SiOxNy; bonding and cleaving the planarized SiOxNyto a quartz plate to form a graymask reticle; etching to remove silicon from the bonded structure; etching to remove SiOxNy and Si3N4 from the bonded structure; and cleaning and drying the graymask reticle.

    Abstract translation: 制造灰度掩模的方法包括制备硅晶片; 在硅晶片上直接沉积一层Si3N4; 将H +离子注入到硅晶片中以形成缺陷层; 在Si 3 N 4层上直接沉积第一层SiOxNy层; 在第一层SiOxNy上直接沉积一层SRO; 图案化和蚀刻SRO层以在SRO层中形成微透镜阵列; 在SRO微透镜阵列上沉积第二层SiOxNy; CMP平面化第二层SiOxNy; 将平面化的SiO x N y键合并切割成石英板以形成灰色掩模掩模; 蚀刻以从结合结构去除硅; 蚀刻从结合结构去除SiOxNy和Si3N4; 并清理并干燥灰色掩模。

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