公开(公告)号：US5096590A

公开(公告)日：1992-03-17

申请号：US762159

申请日：1991-09-18

Applicant: Atsuo Watanabe ,  Mitsutoshi Nakajima ,  Hiroshi Nabetani ,  Yasunori Yamada ,  Tsutomu Ohmori

Inventor： Atsuo Watanabe ,  Mitsutoshi Nakajima ,  Hiroshi Nabetani ,  Yasunori Yamada ,  Tsutomu Ohmori

IPC: B01D61/08 ,  A23L2/08 ,  B01D61/02 ,  B01D61/58

CPC classification number: A23L2/085 ,  B01D61/022

Abstract: Provided is a multistage method and apparatus for concentrating a solution by reverse osmosis, comprising the steps and means for: maximizing the concentration of absolute in a solution in a multistage apparatus having only standard capacity pumps, including steps of providing first concentrating means for concentrating a solution to a first concentration, said first concentrating means comprising at least one concentrating unit which positioned upstream with respect to a direction in which a solution to be concentrated flows, and providing second concentrating means for concentrating the solution that has been concentrated by first concentrating means to a second concentration which is higher than said first concentrating means comprising at least one concentrating unit which is positioned downstream with respect to said direction; said concentrating units comprising consisting essentially of respective membrane modules and respective standard capacity pumps, the membrane module of the concentrating unit of said first concentrating means comprising a tight reverse osmosis membrane with a high rejection percentage sufficient to achieve a high concentration of said solution with a high flux density of solvent flowing through the membrane, and the membrane module of the concentrating unit of said second concentrating means comprising a loose reverse osmosis membrane with a lower rejection percentage sufficient to easily achieve a further concentration of said first concentrating means with a high flux density of solution flowing through the membrane.

公开(公告)号：US5091027A

公开(公告)日：1992-02-25

申请号：US567529

申请日：1990-08-15

Applicant: Atsuo Watanabe

Inventor： Atsuo Watanabe

IPC: B29C63/18 ,  B29D99/00 ,  D21F3/08 ,  D21G1/02 ,  F16C13/00

CPC classification number: D21G1/0246 ,  B29C63/18 ,  B29D99/0035 ,  D21F3/08 ,  D21G1/0233 ,  F16C13/00 ,  B29L2031/324 ,  Y10T156/103 ,  Y10T29/49551

Abstract: A hard roll is produced by a process utilizing the steps of winding a fiber material impregnated with a thermosetting resin around the outer peripheral surface of a metal roll core to form a fiber-reinforced lower winding layer, then injecting a thermosetting synthetic resin material into a mold of predetermined size and curing the material at a specified temperature to form an outer layer hollow cylinder separately from the first step. The next stepsave fitting the outer layer cylinder around the roll core covered with the winding layer, and injecting an adhesive of low viscosity into an annular clearance between the winding layer and the cylinder and then curing the adhesive at a specified temperature to bond the winding layer to the cylinder with the layer of adhesive.

Abstract translation: 通过以下步骤生产硬卷，该方法采用以下步骤：将浸渍有热固性树脂的纤维材料缠绕在金属辊芯的外周表面上，以形成纤维增强的下卷绕层，然后将热固性合成树脂材料注入 预定尺寸的模具，并在特定温度下固化材料以形成与第一步骤分离的外层中空筒体。 下一个步骤将外层圆筒围绕卷绕在卷芯上的辊芯安装，并将低粘度的粘合剂注入到卷绕层和圆筒之间的环形间隙中，然后在特定温度下固化粘合剂以将卷绕层 到气瓶与粘合剂层。

公开(公告)号：US5049967A

公开(公告)日：1991-09-17

申请号：US631907

申请日：1990-12-21

Applicant: Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

Inventor： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

IPC: H01L27/08 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/118 ,  H01L29/68 ,  H01L29/78

CPC classification number: H01L27/11896 ,  H01L21/8249 ,  H01L27/0623

Abstract: An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from a surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

公开(公告)号：US4368568A

公开(公告)日：1983-01-18

申请号：US174244

申请日：1980-07-31

Applicant: Atsuo Watanabe

Inventor： Atsuo Watanabe

IPC: B29C57/00 ,  B29C67/00 ,  B29C70/06 ,  B29D99/00 ,  B32B15/095 ,  B32B27/20 ,  D06B23/02 ,  D06F67/02 ,  D21F3/08 ,  F16C13/00 ,  B21B31/08

CPC classification number: D06B23/026 ,  B29D99/0035 ,  D06F67/02 ,  D21F3/08 ,  F16C13/00 ,  B29L2031/324

Abstract: A polyurethane rubber covered roll comprises a metallic roll core, a reinforcing layer adhering to the outer surface of the roll core, and formed by a nonwoven fabric impregnated with a mixture of a thermosetting resin and a fine inorganic powder, and a layer of polyurethane rubber united integrally with the outer surface of the reinforcing layer. The roll is useful when used, for example, in a paper machine.

Abstract translation: 聚氨酯橡胶覆盖辊包括金属辊芯，附着在辊芯外表面上的增强层，并且由浸渍有热固性树脂和无机细粉末的混合物的无纺布形成，并且由聚氨酯橡胶层 与加强层的外表面整体结合。 当在例如造纸机中使用时，该卷是有用的。

公开(公告)号：US07704350B2

公开(公告)日：2010-04-27

申请号：US10571228

申请日：2004-09-01

Applicant: Takahisa Hikita ,  Atsuo Watanabe

Inventor： Takahisa Hikita ,  Atsuo Watanabe

IPC: D21F3/02 ,  B30B3/02 ,  B30B5/04

CPC classification number: D21F3/0218 ,  D21F3/0227 ,  Y10S162/901 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T442/2369 ,  Y10T442/3854

Abstract: A press belt (2) comprises both-end corresponding regions B positioned so as to correspond to both ends of a press roll (1) or a press shoe (3) in a width direction and having a small thickness and a center region A positioned between the both-end corresponding regions B and having a thickness larger than that of the both-end corresponding region B.

Abstract translation: 压榨带（2）包括两端对应的区域B，其定位成对应于压榨辊（1）或压板（3）在宽度方向上的两端并且具有小的厚度并且中心区域A定位 在两端对应区域B之间，其厚度大于两端对应区域B的厚度。

公开(公告)号：US20090115506A1

公开(公告)日：2009-05-07

申请号：US12345049

申请日：2008-12-29

Applicant: Fumio Murabayashi ,  Takashi Sase ,  Mutsumi Kikuchi ,  Atsuo Watanabe ,  Masatsugu Amishiro ,  Kenji Tabuchi

Inventor： Fumio Murabayashi ,  Takashi Sase ,  Mutsumi Kikuchi ,  Atsuo Watanabe ,  Masatsugu Amishiro ,  Kenji Tabuchi

IPC: H03F1/50

CPC classification number: H01L21/76283 ,  G05B19/0428 ,  G05B2219/25428 ,  G05B2219/25462 ,  H01L27/0629 ,  H04L25/0266

Abstract: A first converter circuit converts a state signal, whose level is constant or slowly varies during a predetermine period of time, into a pulse signal to allow the signal to propagate across an electrically insulating area. A second converter circuit converts the pulse signal, which has propagated through an insulating circuit, into the original state signal or a signal having the same characteristics as the original state signal.

Abstract translation: 第一转换器电路将预定时间段内的电平恒定或缓慢变化的状态信号转换成脉冲信号，以允许信号通过电绝缘区域传播。 第二转换器电路将已经通过绝缘电路传播的脉冲信号转换成原始状态信号或具有与原始状态信号相同特性的信号。

公开(公告)号：US07307313B2

公开(公告)日：2007-12-11

申请号：US11206212

申请日：2005-08-18

Applicant: Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Rajesh Kumar Malhan

Inventor： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Rajesh Kumar Malhan

IPC: H01L29/76

CPC classification number: H01L29/1066 ,  H01L29/7722 ,  H01L29/8083

Abstract: A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.

Abstract translation: 半导体器件包括（a）垂直场效应晶体管，垂直场效应晶体管包括形成在第一导电类型的半导体的第一表面上的漏电极，由半导体的第二表面形成的一对第一沟槽， 沿着第一沟槽分别形成的第二导电类型的控制区域，沿着第一沟槽之间的半导体的第二表面形成的第一导电类型的源极区域，与源极区域连接的源极电极和与源极区域相邻的栅电极 控制区域，（b）与场效应晶体管独立地由半导体的第二表面形成的一对第二沟槽，（c）沿着第二沟槽形成的第二导电类型的控制区，以及（d）二极管， 在第二沟槽之间的第二表面上形成的结。

公开(公告)号：US07289553B2

公开(公告)日：2007-10-30

申请号：US10377670

申请日：2003-03-04

Applicant: Seigoh Yukutake ,  Yasuyuki Kojima ,  Minehiro Nemoto ,  Masatsugu Amishiro ,  Takayuki Iwasaki ,  Shinichiro Mitani ,  Katsuhiro Furukawa ,  Chiyoshi Kamada ,  Atsuo Watanabe ,  Takayuki Oouchi ,  Nobuyasu Kanekawa

Inventor： Seigoh Yukutake ,  Yasuyuki Kojima ,  Minehiro Nemoto ,  Masatsugu Amishiro ,  Takayuki Iwasaki ,  Shinichiro Mitani ,  Katsuhiro Furukawa ,  Chiyoshi Kamada ,  Atsuo Watanabe ,  Takayuki Oouchi ,  Nobuyasu Kanekawa

IPC: H04B1/38 ,  H01L29/00

CPC classification number: H04L25/0266 ,  H01L2924/0002 ,  H04L25/0268 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L27/0002 ,  H04M11/06 ,  H01L2924/00

Abstract: A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.

公开(公告)号：US20070210408A1

公开(公告)日：2007-09-13

申请号：US11684032

申请日：2007-03-09

Applicant: Atsuo Watanabe ,  Mitsutoshi Honda ,  Norio Ishitsuka ,  Masahiro Ito ,  Toshihito Tabata ,  Shinichi Kurita ,  Hidekazu Kamioka

Inventor： Atsuo Watanabe ,  Mitsutoshi Honda ,  Norio Ishitsuka ,  Masahiro Ito ,  Toshihito Tabata ,  Shinichi Kurita ,  Hidekazu Kamioka

IPC: H01L29/00

CPC classification number: H01L21/76286 ,  H01L29/7394 ,  H01L29/7824

Abstract: It is an object of the present invention to provide an integrated circuit device structured to uniformly apply a voltage to side oxide films formed in a trench at both sides in an SOI substrate.The semiconductor integrated circuit device of the present invention comprises a substrate which supports a first insulation layer below an active device region, trench formed in the active device region to come into contact with the first insulation layer, second insulation film formed on the trench side wall, polycrystalline silicon with which the trench is filled, and third insulation film formed on the polycrystalline silicon, wherein the thickness ratio of the third insulation film to the first insulation film is 0.25 or more to uniformly apply a voltage to the oxide insulation films formed in the trench at both sides.It is another object of the present invention to provide a dielectrically isolated semiconductor device of high reliability by realizing a fine and deep element isolating region which can prevent dislocation of an oxide film as an insulation layer by oxidation-induced stress. It is still another object to provide a process for fabrication of the above device.The dielectrically isolated semiconductor device of the present invention comprises a substrate supporting single-crystalline silicon via an oxide film (SOI substrate), the substrate supporting an active element layer deeper than an expanded distance of a depletion layer subjected to the highest voltage applied to the device, and element isolating region which encloses the active element layer. The element isolating region contains a deep trench which comes into contact with the insulation layer on the SOI substrate, and is filled with n heavily doped layers on both side walls, second insulation films each adjacent to the n heavily doped layer and polycrystalline semiconductor layer formed between the second insulation films.

公开(公告)号：US07256453B2

公开(公告)日：2007-08-14

申请号：US11038929

申请日：2005-01-18

Applicant: Hidekatsu Onose ,  Atsuo Watanabe

Inventor： Hidekatsu Onose ,  Atsuo Watanabe

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L29/1066 ,  H01L29/7722 ,  H01L29/808

Abstract: A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the structure is built such that the p+ gate and an n+ source are contiguous. An insulating film is formed on the surface of an n− channel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.

Abstract translation: 提供了一种确保低导通电阻和更好的阻塞效果的结构。 在其中第一区被用作栅极的横向型SIT（静态感应晶体管）中，并且栅极电极形成在第一区域的底部上，构造为使得p ^{+ 门和n + 源是连续的。 在n通道的表面上形成绝缘膜，在绝缘膜上形成辅助栅电极。 此外，辅助栅电极和源电极短路。}