公开(公告)号：US20230268444A1

公开(公告)日：2023-08-24

申请号：US17922034

申请日：2021-11-02

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  South China University of Technology

Inventor： Guangcai YUAN ,  Linfeng LAN ,  Fengjuan LIU ,  Ce NING ,  Hehe HU ,  Fei WANG ,  Junbiao PENG

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/66969

Abstract: A metal oxide semiconductor material includes a semiconductor base material and at least one kind of rare earth compound doped in the semiconductor base material, Each kind of rare earth compound has a general formula represented as (MFD)aAb, where in s the general formula (MFD)aAb, MFD is an element selected from rare earth elements capable of undergoing f-d transition and/or charge transfer transition, A is selected from elements capable of stretching a wavelength range of an absorption spectrum of MFD capable of undergoing the f-d transition and/or the charge transfer transition towards red light into a visible light range, a is a number of the element MFD in the general formula (MFD)aAb, and b is a number of the element A in the general formula (MFD)aAb.

公开(公告)号：US20230079382A1

公开(公告)日：2023-03-16

申请号：US17612225

申请日：2021-02-01

Applicant: BOE Technology Group Co., Ltd.

Inventor： Feng GUAN ,  Guangcai YUAN ,  Xue DONG ,  Ce NING

IPC: H01L27/12

Abstract: Provided are a driving backplane, a method for manufacturing the same and a display device. The driving backplane includes a substrate, a first gate disposed on a side of the substrate, an active layer disposed on a side of the first gate away from the substrate, and a second gate disposed on a side of the active layer away from the substrate. An orthographic projection of the second gate on the substrate is located in an orthographic projection of the first gate on the substrate, and in a direction parallel to the substrate, an edge of an orthographic projection of the first gate on the substrate extends beyond an edge of the orthographic projection of the second gate on the substrate.

公开(公告)号：US20220375966A1

公开(公告)日：2022-11-24

申请号：US17772234

申请日：2021-05-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xue DONG ,  Guangcai YUAN ,  Ce NING ,  Zhiwei LIANG ,  Feng GUAN ,  Zhaohui QIANG ,  Yingwei LIU ,  Ke WANG ,  Zhanfeng CAO

IPC: H01L27/12 ,  H01L23/00

Abstract: An array substrate includes a base substrate, a driving circuit layer, and a functional device layer which are sequentially stacked; the driving circuit layer is provided with first driving circuits, and each first driving circuit at least comprises a driving transistor; and the driving circuit layer comprises a first gate layer, a first gate insulation layer, a semiconductor layer, a second gate insulation layer, a second gate layer, an interlayer dielectric layer, and a source-drain metal layer which are sequentially stacked on one side of the base substrate.

公开(公告)号：US20220208070A1

公开(公告)日：2022-06-30

申请号：US17535127

申请日：2021-11-24

Applicant: BOE Technology Group Co., Ltd.

Inventor： Shuilang DONG ,  Shanshan XU ,  Guangcai YUAN ,  Zhanfeng CAO ,  Ce NING ,  Lizhong WANG ,  Dapeng XUE ,  Nianqi YAO

IPC: G09G3/20

Abstract: A shift register unit includes an input sub-circuit, a pull-down node driving sub-circuit and an output sub-circuit. The pull-down node driving sub-circuit includes a first connection unit, a first voltage-reduction unit and a second connection unit, and configured to: under the control of the first voltage signal terminal and the pull-up node, transmit a first voltage signal from the first voltage signal terminal to the first pull-down node via the first connection unit, and reduce a voltage applied to the second connection unit via the first voltage-reduction unit; and transmit a second voltage signal from the second voltage signal terminal to the first pull-down node via the second connection unit under the control of the pull-up node.

公开(公告)号：US20190233299A1

公开(公告)日：2019-08-01

申请号：US16344000

申请日：2018-09-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wenlin ZHANG ,  Ce NING ,  Hehe HU ,  Zhengliang LI

IPC: C01G15/00 ,  H01L29/786

CPC classification number: C01G15/006 ,  C01P2002/72 ,  C01P2004/61 ,  H01L29/7869

Abstract: An oxide semiconductor composition for use in thin film transistors includes indium oxide, zinc oxide, and an oxide including a doping element of scandium, such as scandium oxide. A molar percentage of the indium oxide can be larger than approximately 50%. The oxide semiconductor composition can have a formula of In2Sc2ZnO7. Manufacturing of the oxide semiconductor composition can include: mixing indium oxide powder, scandium oxide powder, and zinc oxide powder to thereby obtain an oxide shaped object; and sintering the oxide shaped object to form the oxide semiconductor composition. A thin-film transistor for use in a semiconductor device, such as a display apparatus, can include the oxide semiconductor composition, and can thereby have improved mobility of the oxide semiconductor due to the reduced oxygen vacancy therein.

公开(公告)号：US20180247833A1

公开(公告)日：2018-08-30

申请号：US15569728

申请日：2017-04-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ce NING ,  Wei YANG

IPC: H01L21/477 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/477 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/7869

Abstract: A method for fabricating an array substrate is disclosed. The method comprises: forming a first oxide semiconductor active layer of a first TFT in a GOA area of a substrate; performing a first annealing process on the first oxide semiconductor active layer at a first temperature; forming a first insulating layer which covers the first oxide semiconductor active layer; performing a second annealing process on the first oxide semiconductor active layer at a second temperature, wherein the second temperature is lower than the first temperature. This improves a forward bias stability of the first TFT and increases the device lifetime.

公开(公告)号：US20170294454A1

公开(公告)日：2017-10-12

申请号：US15324909

申请日：2015-10-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD

Inventor： Ce NING ,  Wei YANG

IPC: H01L27/12 ,  G02F1/1368

CPC classification number: H01L27/1225 ,  G02F1/1368 ,  G02F2001/134372 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1259 ,  H01L27/127 ,  H01L27/1288

Abstract: The present disclosure provides an array substrate and fabricating method thereof, a display panel, and a display apparatus. A first active layer and common electrodes are formed on the substrate. A first gate insulating layer is formed on the first active layer. A gate electrode is formed on the first gate insulating layer. A second gate insulating layer is formed on he common electrodes and the gate electrode. Via-holes are formed in the second gate insulating layer to expose surface portions of the common electrodes. Source/drain electrodes are formed and electrically connected to the coma on electrodes through the via-holes. A second active layer and pixel electrodes are formed on the second gate insulating layer.

公开(公告)号：US20170040342A1

公开(公告)日：2017-02-09

申请号：US14911213

申请日：2015-07-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ce NING ,  Mingchao LI ,  Fangzhen ZHANG

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/40 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1259 ,  H01L29/401 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/7869

Abstract: The present disclosure relates to the field of display technology and provides a method for manufacturing a TFT, the TFT, an array substrate including the TFT, and a display device. The method includes steps of forming a pattern of a gate electrode on a base substrate, forming a gate insulation layer on the base substrate, and forming patterns of a source electrode and a drain electrode arranged above the gate insulation layer. The method further includes forming an antioxidation metal protection layer on a surface or surfaces of the gate electrode, the source electrode and/or the drain electrode.

Abstract translation: 本公开涉及显示技术领域，并且提供了制造TFT，TFT，包括TFT的阵列基板和显示装置的方法。 该方法包括以下步骤：在基底基板上形成栅极电极的图案，在基底基板上形成栅极绝缘层，以及形成设置在栅极绝缘层上方的源电极和漏电极的图案。 该方法还包括在栅电极，源电极和/或漏电极的表面上形成抗氧化金属保护层。

公开(公告)号：US20160359053A1

公开(公告)日：2016-12-08

申请号：US15156858

申请日：2016-05-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ke WANG ,  Ce NING

IPC: H01L29/786 ,  H01L29/24 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/3272 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78696

Abstract: An oxide thin-film transistor, an array substrate and methods for manufacturing the same, and a display device are provided. The method for manufacturing the oxide thin-film transistor includes: forming a pattern of an oxide semi-conductor layer above a base substrate; and illuminating, by a light source, two opposite boundary regions of the pattern of the oxide semi-conductor layer, where the illuminated two opposite boundary regions of the pattern of the oxide semi-conductor layer form ohmic contact layers and a region of the pattern of the oxide semi-conductor layer that is not illuminated forms a semi-conductor active layer; forming a source electrode and a drain electrode which are connected to the semi-conductor active layer via the ohmic contact layers respectively.

Abstract translation: 提供氧化物薄膜晶体管，阵列基板及其制造方法以及显示装置。 氧化物薄膜晶体管的制造方法包括：在基底基板上形成氧化物半导体层的图案; 并且通过光源照射氧化物半导体层的图案的两个相对的边界区域，其中氧化物半导体层的图案的被照射的两个相对的边界区域形成欧姆接触层和图案的区域 未被照射的氧化物半导体层形成半导体有源层; 形成源电极和漏电极，分别经由欧姆接触层与半导体有源层连接。