公开(公告)号：US20080277735A1

公开(公告)日：2008-11-13

申请号：US11800615

申请日：2007-05-07

申请人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Ta-Ming Kuan ,  Wen-Chin Lee

发明人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Ta-Ming Kuan ,  Wen-Chin Lee

IPC分类号： H01L29/417 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region.

摘要翻译： 半导体结构包括半导体衬底; 半导体衬底上的栅极电介质; 位于栅极电介质上的栅电极; 与栅电极相邻的深源/漏区; 深源/漏区上的硅化物区; 以及在硅化物区域和栅电极之间的升高的金属化源极/漏极区域。 升高的金属化源极/漏极区域邻接硅化物区域。

公开(公告)号：US20080145984A1

公开(公告)日：2008-06-19

申请号：US11640713

申请日：2006-12-18

申请人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

发明人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843

摘要： A method for forming a semiconductor structure includes: providing a semiconductor substrate; forming an NMOS device at a surface of the semiconductor substrate, which comprises forming a first source/drain electrode on a first source/drain region of the NMOS device, wherein the first source/drain electrode has a first barrier height; forming a PMOS device at the surface of the semiconductor substrate comprising forming a second source/drain electrode on a second source/drain region of the PMOS device, wherein the second source/drain electrode has a second barrier height, and wherein the first barrier height is different from the second barrier height; forming a first stressed film having a first intrinsic stress over the NMOS device; and forming a second stressed film having a second intrinsic stress over the PMOS device, wherein the first intrinsic stress is more tensile than the second intrinsic stress.

摘要翻译： 一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底的表面上形成NMOS器件，其包括在所述NMOS器件的第一源极/漏极区域上形成第一源极/漏极，其中所述第一源极/漏极具有第一势垒高度; 在所述半导体衬底的表面上形成PMOS器件，包括在所述PMOS器件的第二源极/漏极区域上形成第二源极/漏极电极，其中所述第二源极/漏极具有第二势垒高度，并且其中所述第一势垒高度 与第二屏障高度不同; 在NMOS器件上形成具有第一固有应力的第一应力膜; 以及在所述PMOS器件上形成具有第二固有应力的第二应力膜，其中所述第一本征应力比所述第二固有应力更具拉伸力。

公开(公告)号：US07355262B2

公开(公告)日：2008-04-08

申请号：US11378907

申请日：2006-03-17

申请人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

发明人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

IPC分类号： H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L21/76224 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1037 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on the semiconductor substrate, and forming a MOS device in the diffusion region. The DTE causes silicon migration, forming a rounded or a T-shaped surface of the diffusion regions. The method may further include recessing a portion of the diffusion region before performing the DTE. The diffusion region has a slanted surface after performing the DTE.

摘要翻译： 半导体结构使用扩散地形工程（DTE）形成。 优选的方法包括提供半导体衬底，形成限定扩散区域的沟槽隔离区域，在半导体衬底上的含氢环境中进行DTE，以及在扩散区域中形成MOS器件。 DTE导致硅迁移，形成扩散区域的圆形或T形表面。 该方法还可以包括在执行DTE之前使扩散区的一部分凹陷。 在执行DTE之后，扩散区域具有倾斜表面。

公开(公告)号：US07321155B2

公开(公告)日：2008-01-22

申请号：US10840911

申请日：2004-05-06

申请人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

发明人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

IPC分类号： H01L29/772

CPC分类号： H01L29/7845 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  Y10S257/90

摘要： A strained channel transistor and method for forming the same, the strained channel transistor including a semiconductor substrate; a gate dielectric overlying a channel region; a gate electrode overlying the gate dielectric; source drain extension (SDE) regions and source and drain (S/D) regions; wherein a stressed dielectric portion selected from the group consisting of a pair of stressed offset spacers disposed adjacent the gate electrode and a stressed dielectric layer disposed over the gate electrode including the S/D regions is disposed to exert a strain on a channel region.

摘要翻译： 应变沟道晶体管及其形成方法，所述应变沟道晶体管包括半导体衬底; 覆盖沟道区的栅极电介质; 覆盖栅极电介质的栅电极; 源极扩展（SDE）区域和源极和漏极（S / D）区域; 其特征在于，设置有选自由邻近所述栅电极配置的一对应力偏置间隔物和设置在包括所述S / D区域的所述栅极上方的应力介电层的应力电介质部分，以在沟道区域上施加应变。

公开(公告)号：US20070215936A1

公开(公告)日：2007-09-20

申请号：US11378907

申请日：2006-03-17

申请人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

发明人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L21/76224 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1037 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on the semiconductor substrate, and forming a MOS device in the diffusion region. The DTE causes silicon migration, forming a rounded or a T-shaped surface of the diffusion regions. The method may further include recessing a portion of the diffusion region before performing the DTE. The diffusion region has a slanted surface after performing the DTE.

摘要翻译： 半导体结构使用扩散地形工程（DTE）形成。 优选的方法包括提供半导体衬底，形成限定扩散区域的沟槽隔离区域，在半导体衬底上的含氢环境中进行DTE，以及在扩散区域中形成MOS器件。 DTE导致硅迁移，形成扩散区域的圆形或T形表面。 该方法还可以包括在执行DTE之前使扩散区的一部分凹陷。 在执行DTE之后，扩散区域具有倾斜表面。

公开(公告)号：US20090140351A1

公开(公告)日：2009-06-04

申请号：US11948823

申请日：2007-11-30

申请人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

发明人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/6656 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming a slim spacer on sidewalls of the gate dielectric and the gate electrode; forming a silicon carbon (SiC) region adjacent the slim spacer; forming a deep source/drain region comprising at least a portion of the silicon carbon region; blanket forming a metal layer, wherein a first interface between the metal layer and the deep source/drain is higher than a second interface between the gate dielectric and the semiconductor substrate; and annealing the semiconductor device to form a silicide region. Preferably, a horizontal spacing between an inner edge of the silicide region and a respective edge of the gate electrode is preferably less than about 150 Å.

摘要翻译： 一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅极电介质和所述栅电极的侧壁上形成细长间隔物; 形成邻近细长间隔物的硅碳（SiC）区域; 形成包含所述硅碳区域的至少一部分的深源极/漏极区域; 毯形成金属层，其中金属层和深源极/漏极之间的第一界面高于栅极电介质和半导体衬底之间的第二界面; 并对半导体器件进行退火以形成硅化物区域。 优选地，硅化物区域的内边缘和栅电极的相应边缘之间的水平间隔优选小于约150埃。

公开(公告)号：US20090117695A1

公开(公告)日：2009-05-07

申请号：US12260674

申请日：2008-10-29

申请人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

发明人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC分类号： H01L21/8249

CPC分类号： H01L21/8249 ,  H01L21/823807 ,  H01L27/0623 ,  H01L29/7843

摘要： A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

摘要翻译： 提供了通过机械单轴应变增强性能的BiCMOS器件。 本发明的第一实施例包括形成在衬底的不同区域上的NMOS晶体管，PMOS晶体管和双极晶体管。 具有拉伸应力的第一接触蚀刻停止层形成在NMOS晶体管上，并且在PMOS晶体管和双极晶体管上形成具有压应力的第二接触蚀刻停止层，从而允许每个器件的增强。 除了应力接触蚀刻停止层之外，另一实施例还包括PMOS晶体管和NMOS晶体管中的应变通道区域以及BJT中的应变基极。

公开(公告)号：US20060125121A1

公开(公告)日：2006-06-15

申请号：US11081416

申请日：2005-03-16

申请人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi ,  Chung-Hu Ke

发明人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi ,  Chung-Hu Ke

IPC分类号： H01L31/109

CPC分类号： H01L27/095 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844 ,  H01L29/7841 ,  H01L29/812

摘要： A tunneling injection based Schottky source/drain memory cell comprising: a first semiconductor layer with a first conductivity type overlying an insulating layer, wherein the first semiconductor acts as a body region; a gate dielectric overlying the semiconductor layer; a gate electrode overlying the gate dielectric; a pair of spacers on sides of the gate electrodes; and a first Schottky barrier junction formed on a source region and a second Schottky barrier junction formed on a drain region on opposing sides of the body region. The source and the regions have an overlapping portion with the gate electrode and length of overlapping portion is preferably greater than about 5 Å. Interfacial layers are formed between the first and the second Schottky barrier regions.

摘要翻译： 一种基于隧道注入的肖特基源/漏存储单元，包括：第一半导体层，其具有覆盖绝缘层的第一导电类型，其中所述第一半导体作为体区; 覆盖半导体层的栅极电介质; 覆盖栅极电介质的栅电极; 栅电极侧面的一对间隔物; 以及形成在源区域上的第一肖特基势垒结和形成在身体区域的相对侧上的漏极区域上的第二肖特基势垒结。 源极和区域与栅电极具有重叠部分，并且重叠部分的长度优选大于约。 在第一和第二肖特基势垒区之间形成界面层。

公开(公告)号：US20050247986A1

公开(公告)日：2005-11-10

申请号：US10840911

申请日：2004-05-06

申请人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

发明人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/7845 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  Y10S257/90

摘要： A strained channel transistor and method for forming the the strained channel transistor including a semiconductor rate; a gate dielectric overlying a channel region; a gate rode overlying the gate dielectric; source drain extension regions and source and drain (S/D) regions; wherein a sed dielectric portion selected from the group consisting of r of stressed offset spacers disposed adjacent the gate rode and a stressed dielectric layer disposed over the gate rode including the S/D regions is disposed to exert a strain channel region.

摘要翻译： 一种应变通道晶体管和用于形成包括半导体速率的应变通道晶体管的方法; 覆盖沟道区的栅极电介质; 栅极覆盖栅极电介质; 源极漏极延伸区域和源极和漏极（S / D）区域; 其中设置选自由围绕所述栅极环配置的应力偏移间隔的r和设置在包括所述S / D区的所述栅极周围的应力介电层的施放电介质部分以施加应变通道区域。

公开(公告)号：US20050151166A1

公开(公告)日：2005-07-14

申请号：US10835100

申请日：2004-04-29

申请人： Chun-Chieh Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

发明人： Chun-Chieh Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L27/092 ,  H01L27/10 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a metal contact is provided. In the preferred embodiment, a metal contact is provided through an interlayer dielectric and is in electrical contact with a metal structure, such as a metal gate electrode of a transistor. A conductive layer is provided between the metal contact and the metal structure. The conductive layer provides one or more of a barrier layer, an adhesion layer, or an etch stop layer. The conductive layer is preferably an elemental metal, metal alloy, metal nitride, metal oxide, or a combination thereof. In an alternative embodiment, the conductive layer is formed of polysilicon.

摘要翻译： 提供具有金属接触的半导体器件。 在优选实施例中，通过层间电介质提供金属接触，并与诸如晶体管的金属栅电极的金属结构电接触。 在金属接触件和金属结构之间设置导电层。 导电层提供阻挡层，粘合层或蚀刻停止层中的一个或多个。 导电层优选为元素金属，金属合金，金属氮化物，金属氧化物或其组合。 在替代实施例中，导电层由多晶硅形成。